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| author | Michael Abed <michaelabed@gmail.com> | 2012-03-28 09:58:28 -0400 |
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| committer | Michael Abed <michaelabed@gmail.com> | 2012-03-28 09:58:28 -0400 |
| commit | 5d32d4ca9aaf2000e05503457bed1b8f04ca6d62 (patch) | |
| tree | 1b1d1ff3a6645fd208ae19918d064e2056777e52 /_xmsgs | |
| download | ec311-lab5-5d32d4ca9aaf2000e05503457bed1b8f04ca6d62.tar.gz ec311-lab5-5d32d4ca9aaf2000e05503457bed1b8f04ca6d62.tar.bz2 ec311-lab5-5d32d4ca9aaf2000e05503457bed1b8f04ca6d62.zip | |
initial commit
Diffstat (limited to '_xmsgs')
| -rw-r--r-- | _xmsgs/pn_parser.xmsgs | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..278dafe --- /dev/null +++ b/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated --> +<!-- by the Xilinx ISE software. Any direct editing or --> +<!-- changes made to this file may result in unpredictable --> +<!-- behavior or data corruption. It is strongly advised that --> +<!-- users do not edit the contents of this file. --> +<!-- --> +<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> + +<messages> +<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/michael/Documents/School/EC311/lab5/DisplayController.v" into library work</arg> +</msg> + +</messages> + |