diff options
| author | Michael Abed <michaelabed@gmail.com> | 2012-03-29 16:17:45 -0400 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-03-29 16:17:45 -0400 |
| commit | 9540811daaffad7811475ea584333ab633ba8508 (patch) | |
| tree | 9c20071e05b1225f9b466dede6236a7cd53ea851 /lab5.gise | |
| parent | f9328ba21afde12326c04e59eb542446faf5fae4 (diff) | |
| download | ec311-lab5-master.tar.gz ec311-lab5-master.tar.bz2 ec311-lab5-master.zip | |
Diffstat (limited to 'lab5.gise')
| -rw-r--r-- | lab5.gise | 92 |
1 files changed, 90 insertions, 2 deletions
@@ -21,8 +21,96 @@ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="lab5.xise"/>
- <files xmlns="http://www.xilinx.com/XMLSchema"/>
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="TEST_Bin2BCD_isim_beh.exe"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="TEST_DisplayController_isim_beh.exe"/>
+ <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="TEST_FirFilter_beh.prj"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="TEST_FirFilter_isim_beh.exe"/>
+ <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="TEST_FirFilter_isim_beh.wdb"/>
+ <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
+ </files>
- <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">
+ <transform xil_pn:end_ts="1333048801" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1333048801">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1333049488" xil_pn:in_ck="2732522951227592992" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333049488">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="InputChanged"/>
+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="Bin2BCD.v"/>
+ <outfile xil_pn:name="ClockDivider.v"/>
+ <outfile xil_pn:name="DisplayController.v"/>
+ <outfile xil_pn:name="FIRController.v"/>
+ <outfile xil_pn:name="FIRFilter.v"/>
+ <outfile xil_pn:name="SevSegDisp.v"/>
+ <outfile xil_pn:name="TEST_Bin2BCD.v"/>
+ <outfile xil_pn:name="TEST_DisplayController.v"/>
+ <outfile xil_pn:name="TEST_FirFilter.v"/>
+ </transform>
+ <transform xil_pn:end_ts="1333049488" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8794436030188559171" xil_pn:start_ts="1333049488">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1333049488" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5025297475059373691" xil_pn:start_ts="1333049488">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1333048801" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="2765485881546830441" xil_pn:start_ts="1333048801">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1333049488" xil_pn:in_ck="2732522951227592992" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333049488">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="InputChanged"/>
+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="Bin2BCD.v"/>
+ <outfile xil_pn:name="ClockDivider.v"/>
+ <outfile xil_pn:name="DisplayController.v"/>
+ <outfile xil_pn:name="FIRController.v"/>
+ <outfile xil_pn:name="FIRFilter.v"/>
+ <outfile xil_pn:name="SevSegDisp.v"/>
+ <outfile xil_pn:name="TEST_Bin2BCD.v"/>
+ <outfile xil_pn:name="TEST_DisplayController.v"/>
+ <outfile xil_pn:name="TEST_FirFilter.v"/>
+ </transform>
+ <transform xil_pn:end_ts="1333049490" xil_pn:in_ck="2732522951227592992" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6294440187011869753" xil_pn:start_ts="1333049488">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="InputChanged"/>
+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="TEST_FirFilter_beh.prj"/>
+ <outfile xil_pn:name="TEST_FirFilter_isim_beh.exe"/>
+ <outfile xil_pn:name="fuse.log"/>
+ <outfile xil_pn:name="isim"/>
+ <outfile xil_pn:name="isim.log"/>
+ <outfile xil_pn:name="xilinxsim.ini"/>
+ </transform>
+ <transform xil_pn:end_ts="1333049490" xil_pn:in_ck="-4992000523088231073" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4694054843649941820" xil_pn:start_ts="1333049490">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="TEST_FirFilter_isim_beh.wdb"/>
+ <outfile xil_pn:name="isim.cmd"/>
+ <outfile xil_pn:name="isim.log"/>
+ </transform>
+ </transforms>
</generated_project>
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