diff options
87 files changed, 3818 insertions, 73 deletions
diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..d40292e --- /dev/null +++ b/.gitignore @@ -0,0 +1,3 @@ + +*.un~ + diff --git a/DisplayController.v b/DisplayController.v index 6da8227..8d9a77a 100644 --- a/DisplayController.v +++ b/DisplayController.v @@ -36,7 +36,7 @@ reg [3:0] AN; wire clkdiv; reg [1:0] w = 2'd0; -ClockDivider cdiv(.clk_out(clkdiv), .rst(rst), .clk_in(clk), .count(500_000)); +ClockDivider cdiv(.clk_out(clkdiv), .rst(rst), .clk_in(clk), .count(10)); wire [6:0] o1, o2, o3, o4; diff --git a/DisplayController_summary.html b/DisplayController_summary.html index e3bd536..5983289 100644 --- a/DisplayController_summary.html +++ b/DisplayController_summary.html @@ -7,11 +7,11 @@ <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> <TD>lab5.xise</TD> <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> -<TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab5/_xmsgs/pn_parser.xmsgs?&DataKey=Error'>1 Error</A></TD> +<TD> No Errors </TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> -<TD>DisplayController</TD> +<TD>FIRController</TD> <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> <TD>New</TD> </TR> @@ -75,5 +75,5 @@ </TABLE> -<br><center><b>Date Generated:</b> 03/27/2012 - 16:53:37</center> +<br><center><b>Date Generated:</b> 03/29/2012 - 15:16:18</center> </BODY></HTML>
\ No newline at end of file diff --git a/FIRFilter.v b/FIRFilter.v index dada832..61c0ef8 100644 --- a/FIRFilter.v +++ b/FIRFilter.v @@ -27,16 +27,24 @@ module FIRFilter( reg [15:0] yout; -reg [15:0] yold1; -reg [15:0] yold2; +reg [15:0] yold1=0; +reg [15:0] yold2=0; -always @(*) begin - yout = 20*yin + 15*yold1 + 10*yold2; +always @(yin, yold1, yold2, rst) begin + if (rst) + yout = 0; + else + yout = 20*yin + 15*yold1 + 10*yold2; end -always @(load) begin - yold2 = yold1; - yold1 = yin; +always @(posedge load, posedge rst) begin + if (rst) begin + yold1 = 0; + yold2 = 0; + end else begin + yold2 = yold1; + yold1 = yin; + end end endmodule diff --git a/TEST_Bin2BCD.v b/TEST_Bin2BCD.v new file mode 100644 index 0000000..7561bf6 --- /dev/null +++ b/TEST_Bin2BCD.v @@ -0,0 +1,60 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:26:38 03/29/2012 +// Design Name: Bin2BCD +// Module Name: /home/michael/Documents/School/EC311/lab5/TEST_Bin2BCD.v +// Project Name: lab5 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: Bin2BCD +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_Bin2BCD; + + // Inputs + reg [15:0] bin; + + // Outputs + wire [3:0] one; + wire [3:0] ten; + wire [3:0] hun; + wire [3:0] thous; + + // Instantiate the Unit Under Test (UUT) + Bin2BCD uut ( + .bin(bin), + .one(one), + .ten(ten), + .hun(hun), + .thous(thous) + ); + + initial begin + // Initialize Inputs + bin = 0; + + // Wait 100 ns for global reset to finish + #100; + bin = 7; #50; + bin = 16;#50; + bin = 217;#50; + bin = 1839; #50; + // Add stimulus here + + end + +endmodule + diff --git a/TEST_Bin2BCD_isim_beh.exe b/TEST_Bin2BCD_isim_beh.exe Binary files differnew file mode 100755 index 0000000..beb9ccd --- /dev/null +++ b/TEST_Bin2BCD_isim_beh.exe diff --git a/TEST_DisplayController.v b/TEST_DisplayController.v new file mode 100644 index 0000000..c2c7271 --- /dev/null +++ b/TEST_DisplayController.v @@ -0,0 +1,74 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:17:59 03/29/2012 +// Design Name: DisplayController +// Module Name: /home/michael/Documents/School/EC311/lab5/TEST_DisplayController.v +// Project Name: lab5 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: DisplayController +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_DisplayController; + + // Inputs + reg [3:0] A; + reg [3:0] B; + reg [3:0] C; + reg [3:0] D; + reg clk; + reg rst; + + // Outputs + wire [6:0] ssd; + wire [3:0] AN; + + // Instantiate the Unit Under Test (UUT) + DisplayController uut ( + .A(A), + .B(B), + .C(C), + .D(D), + .clk(clk), + .rst(rst), + .ssd(ssd), + .AN(AN) + ); + + initial begin + // Initialize Inputs + A = 0; + B = 0; + C = 0; + D = 0; + clk = 0; + rst = 0; + + // Wait 100 ns for global reset to finish + #100; + A=4'd3; + B=4'd0; + C=4'd7; + D=4'd9; + while (1) begin + clk = ~clk; #1; + end + // Add stimulus here + + end + +endmodule + diff --git a/TEST_DisplayController_isim_beh.exe b/TEST_DisplayController_isim_beh.exe Binary files differnew file mode 100755 index 0000000..beb9ccd --- /dev/null +++ b/TEST_DisplayController_isim_beh.exe diff --git a/TEST_FirFilter.v b/TEST_FirFilter.v new file mode 100644 index 0000000..fd8454a --- /dev/null +++ b/TEST_FirFilter.v @@ -0,0 +1,60 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:29:29 03/29/2012 +// Design Name: FIRFilter +// Module Name: /home/michael/Documents/School/EC311/lab5/TEST_FirFilter.v +// Project Name: lab5 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: FIRFilter +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_FirFilter; + + // Inputs + reg [7:0] yin; + reg load; + reg rst; + + // Outputs + wire [15:0] yout; + + // Instantiate the Unit Under Test (UUT) + FIRFilter uut ( + .yin(yin), + .yout(yout), + .load(load), + .rst(rst) + ); + + initial begin + // Initialize Inputs + yin = 0; + load = 0; + rst = 0; + + // Wait 100 ns for global reset to finish + #100; + + // Add stimulus here + yin = 100; #10; load = 1; #10 load = 0; #10; + yin = 12; #10; load = 1; #10 load = 0; #10; + yin = 157; #10; load = 1; #10 load = 0; #10; + yin = 56; #10; load = 1; #10 load = 0; #10; + end + +endmodule + diff --git a/TEST_FirFilter_beh.prj b/TEST_FirFilter_beh.prj new file mode 100644 index 0000000..ef59f44 --- /dev/null +++ b/TEST_FirFilter_beh.prj @@ -0,0 +1,3 @@ +verilog work "FIRFilter.v" +verilog work "TEST_FirFilter.v" +verilog work "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" diff --git a/TEST_FirFilter_isim_beh.exe b/TEST_FirFilter_isim_beh.exe Binary files differnew file mode 100755 index 0000000..beb9ccd --- /dev/null +++ b/TEST_FirFilter_isim_beh.exe diff --git a/TEST_FirFilter_isim_beh.wdb b/TEST_FirFilter_isim_beh.wdb Binary files differnew file mode 100644 index 0000000..5755f5a --- /dev/null +++ b/TEST_FirFilter_isim_beh.wdb diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs index 278dafe..4c3d12b 100644 --- a/_xmsgs/pn_parser.xmsgs +++ b/_xmsgs/pn_parser.xmsgs @@ -8,7 +8,7 @@ <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> <messages> -<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/michael/Documents/School/EC311/lab5/DisplayController.v" into library work</arg> +<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/michael/Documents/School/EC311/lab5/FIRFilter.v" into library work</arg> </msg> </messages> diff --git a/firfilter.wcfg b/firfilter.wcfg new file mode 100644 index 0000000..0facbc5 --- /dev/null +++ b/firfilter.wcfg @@ -0,0 +1,38 @@ +<?xml version="1.0" encoding="UTF-8"?> +<wave_config> + <wave_state> + </wave_state> + <db_ref_list> + <db_ref path="/home/michael/Documents/School/EC311/lab5/TEST_FirFilter_isim_beh.wdb" id="1" type="auto"> + <top_modules> + <top_module name="TEST_FirFilter" /> + <top_module name="glbl" /> + </top_modules> + </db_ref> + </db_ref_list> + <WVObjectSize size="6" /> + <wvobject fp_name="/TEST_FirFilter/yout" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">yout[15:0]</obj_property> + <obj_property name="ObjectShortName">yout[15:0]</obj_property> + </wvobject> + <wvobject fp_name="/TEST_FirFilter/yin" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">yin[7:0]</obj_property> + <obj_property name="ObjectShortName">yin[7:0]</obj_property> + </wvobject> + <wvobject fp_name="/TEST_FirFilter/load" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">load</obj_property> + <obj_property name="ObjectShortName">load</obj_property> + </wvobject> + <wvobject fp_name="/TEST_FirFilter/rst" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">rst</obj_property> + <obj_property name="ObjectShortName">rst</obj_property> + </wvobject> + <wvobject fp_name="/TEST_FirFilter/uut/yold1" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">yold1[15:0]</obj_property> + <obj_property name="ObjectShortName">yold1[15:0]</obj_property> + </wvobject> + <wvobject fp_name="/TEST_FirFilter/uut/yold2" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">yold2[15:0]</obj_property> + <obj_property name="ObjectShortName">yold2[15:0]</obj_property> + </wvobject> +</wave_config> diff --git a/fuse.log b/fuse.log new file mode 100644 index 0000000..cfaf0da --- /dev/null +++ b/fuse.log @@ -0,0 +1,23 @@ +Running: /home/michael/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "/home/michael/Documents/School/EC311/lab5/TEST_FirFilter_isim_beh.exe" -prj "/home/michael/Documents/School/EC311/lab5/TEST_FirFilter_beh.prj" "work.TEST_FirFilter" "work.glbl" +ISim O.87xd (signature 0x8ddf5b5d) +Number of CPUs detected in this system: 2 +Turning on mult-threading, number of parallel sub-compilation jobs: 4 +Determining compilation order of HDL files +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab5/FIRFilter.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab5/FIRFilter.v" Line 28: Redeclaration of ansi port yout is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab5/TEST_FirFilter.v" into library work +Analyzing Verilog file "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" into library work +Starting static elaboration +Completed static elaboration +Fuse Memory Usage: 94996 KB +Fuse CPU Usage: 1620 ms +Compiling module FIRFilter +Compiling module TEST_FirFilter +Compiling module glbl +Time Resolution for simulation is 1ps. +Waiting for 1 sub-compilation(s) to finish... +Compiled 3 Verilog Units +Built simulation executable /home/michael/Documents/School/EC311/lab5/TEST_FirFilter_isim_beh.exe +Fuse Memory Usage: 393012 KB +Fuse CPU Usage: 1640 ms +GCC CPU Usage: 300 ms diff --git a/fuse.xmsgs b/fuse.xmsgs new file mode 100644 index 0000000..ec4f168 --- /dev/null +++ b/fuse.xmsgs @@ -0,0 +1,12 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated + by the Xilinx ISE software. Any direct editing or + changes made to this file may result in unpredictable + behavior or data corruption. It is strongly advised that + users do not edit the contents of this file. --> +<messages> +<msg type="warning" file="HDLCompiler" num="751" delta="unknown" >"/home/michael/Documents/School/EC311/lab5/FIRFilter.v" Line 28: Redeclaration of ansi port <arg fmt="%s" index="1">yout</arg> is not allowed +</msg> + +</messages> + diff --git a/fuseRelaunch.cmd b/fuseRelaunch.cmd new file mode 100644 index 0000000..8390901 --- /dev/null +++ b/fuseRelaunch.cmd @@ -0,0 +1 @@ +-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "/home/michael/Documents/School/EC311/lab5/TEST_FirFilter_isim_beh.exe" -prj "/home/michael/Documents/School/EC311/lab5/TEST_FirFilter_beh.prj" "work.TEST_FirFilter" "work.glbl" diff --git a/iseconfig/FIRController.xreport b/iseconfig/FIRController.xreport index 80763e1..70ab327 100644 --- a/iseconfig/FIRController.xreport +++ b/iseconfig/FIRController.xreport @@ -1,11 +1,11 @@ <?xml version='1.0' encoding='UTF-8'?> <report-views version="2.0" > <header> - <DateModified>2012-03-27T16:33:33</DateModified> - <ModuleName>DisplayController</ModuleName> + <DateModified>2012-03-29T15:16:18</DateModified> + <ModuleName>FIRController</ModuleName> <SummaryTimeStamp>Unknown</SummaryTimeStamp> <SavedFilePath>/home/michael/Documents/School/EC311/lab5/iseconfig/FIRController.xreport</SavedFilePath> - <ImplementationReportsDirectory>/home/michael/Documents/School/EC311/lab5</ImplementationReportsDirectory> + <ImplementationReportsDirectory>/home/michael/Documents/School/EC311/lab5/</ImplementationReportsDirectory> <DateInitialized>2012-03-27T16:33:33</DateInitialized> <EnableMessageFiltering>false</EnableMessageFiltering> </header> diff --git a/iseconfig/lab5.projectmgr b/iseconfig/lab5.projectmgr index ce403c0..5788bca 100644 --- a/iseconfig/lab5.projectmgr +++ b/iseconfig/lab5.projectmgr @@ -1,4 +1,4 @@ -<?xml version="1.0" encoding="utf-8"?> +<?xml version='1.0' encoding='utf-8'?> <!--This is an ISE project configuration file.--> <!--It holds project specific layout data for the projectmgr plugin.--> <!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.--> @@ -9,13 +9,13 @@ <ClosedNodesVersion>2</ClosedNodesVersion> </ClosedNodes> <SelectedItems> - <SelectedItem>dc - DisplayController (/home/michael/Documents/School/EC311/lab5/DisplayController.v)</SelectedItem> + <SelectedItem>ff - FIRFilter (/home/michael/Documents/School/EC311/lab5/FIRFilter.v)</SelectedItem> </SelectedItems> - <ScrollbarPosition orientation="vertical" >1</ScrollbarPosition> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000155000000020000000000000000000000000200000064ffffffff000000810000000300000002000001550000000100000003000000000000000100000003</ViewHeaderState> <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> - <CurrentItem>dc - DisplayController (/home/michael/Documents/School/EC311/lab5/DisplayController.v)</CurrentItem> + <CurrentItem>ff - FIRFilter (/home/michael/Documents/School/EC311/lab5/FIRFilter.v)</CurrentItem> </ItemView> <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" > <ClosedNodes> @@ -23,13 +23,13 @@ <ClosedNode>Design Utilities</ClosedNode> </ClosedNodes> <SelectedItems> - <SelectedItem></SelectedItem> + <SelectedItem/> </SelectedItems> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000154000000010000000100000000000000000000000064ffffffff000000810000000000000001000001540000000100000000</ViewHeaderState> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> - <CurrentItem></CurrentItem> + <CurrentItem/> </ItemView> <ItemView guiview="File" > <ClosedNodes> @@ -73,5 +73,49 @@ <CurrentItem></CurrentItem> </ItemView> <SourceProcessView>000000ff00000000000000020000013f0000012001000000060100000002</SourceProcessView> - <CurrentView>Implementation</CurrentView> + <CurrentView>Behavioral Simulation</CurrentView> + <ItemView engineview="BehavioralSim" guiview="Source" compilemo |