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diff --git a/TEST_FirFilter.v b/TEST_FirFilter.v
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+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   15:29:29 03/29/2012
+// Design Name:   FIRFilter
+// Module Name:   /home/michael/Documents/School/EC311/lab5/TEST_FirFilter.v
+// Project Name:  lab5
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: FIRFilter
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module TEST_FirFilter;
+
+	// Inputs
+	reg [7:0] yin;
+	reg load;
+	reg rst;
+
+	// Outputs
+	wire [15:0] yout;
+
+	// Instantiate the Unit Under Test (UUT)
+	FIRFilter uut (
+		.yin(yin), 
+		.yout(yout), 
+		.load(load), 
+		.rst(rst)
+	);
+
+	initial begin
+		// Initialize Inputs
+		yin = 0;
+		load = 0;
+		rst = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+        
+		// Add stimulus here
+		yin = 100; #10; load = 1; #10 load = 0; #10;
+		yin = 12; #10; load = 1; #10 load = 0; #10;
+		yin = 157; #10; load = 1; #10 load = 0; #10;
+		yin = 56; #10; load = 1; #10 load = 0; #10;
+	end
+      
+endmodule
+