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Diffstat (limited to 'fuse.log')
| -rw-r--r-- | fuse.log | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/fuse.log b/fuse.log new file mode 100644 index 0000000..cfaf0da --- /dev/null +++ b/fuse.log @@ -0,0 +1,23 @@ +Running: /home/michael/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "/home/michael/Documents/School/EC311/lab5/TEST_FirFilter_isim_beh.exe" -prj "/home/michael/Documents/School/EC311/lab5/TEST_FirFilter_beh.prj" "work.TEST_FirFilter" "work.glbl" +ISim O.87xd (signature 0x8ddf5b5d) +Number of CPUs detected in this system: 2 +Turning on mult-threading, number of parallel sub-compilation jobs: 4 +Determining compilation order of HDL files +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab5/FIRFilter.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab5/FIRFilter.v" Line 28: Redeclaration of ansi port yout is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab5/TEST_FirFilter.v" into library work +Analyzing Verilog file "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" into library work +Starting static elaboration +Completed static elaboration +Fuse Memory Usage: 94996 KB +Fuse CPU Usage: 1620 ms +Compiling module FIRFilter +Compiling module TEST_FirFilter +Compiling module glbl +Time Resolution for simulation is 1ps. +Waiting for 1 sub-compilation(s) to finish... +Compiled 3 Verilog Units +Built simulation executable /home/michael/Documents/School/EC311/lab5/TEST_FirFilter_isim_beh.exe +Fuse Memory Usage: 393012 KB +Fuse CPU Usage: 1640 ms +GCC CPU Usage: 300 ms |