1 files changed, 66 insertions, 0 deletions
diff --git a/Detector.v b/Detector.v
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:38:26 04/05/2012 
+// Design Name: 
+// Module Name:    Detector 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Detector(
+    input inp,
+    input clk,
+    input rst,
+    output result,
+	 output [1:0] state
+    );
+
+reg [1:0] state;
+reg [1:0] nextstate;
+reg result;
+
+initial begin
+	state = 0;
+	result = 0;
+end
+
+always @(posedge clk or posedge rst)  begin
+	if (rst) begin
+		state <= 0;
+	 end else begin
+		state <= nextstate;
+	end
+end
+
+always @(*) begin
+	case (state)
+		2'b00: nextstate = inp ? 2'b01 : 2'b00;
+		2'b01: nextstate = inp ? 2'b10 : 2'b00;
+		2'b10: nextstate = inp ? 2'b11 : 2'b00;
+		2'b11: nextstate = inp ? 2'b11 : 2'b00;
+		default: nextstate = 2'b00;
+	endcase
+end
+
+always @(state) begin
+	case (state)
+		2'b00: result = 0;
+		2'b01: result = 0;
+		2'b10: result = 0;
+		2'b11: result = 1;
+		default: result = 0;
+	endcase
+end
+
+endmodule