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-rw-r--r--ClockDivider.v47
-rw-r--r--Detector.v66
-rw-r--r--Detector_summary.html79
-rw-r--r--DisplayController.v48
-rw-r--r--FSMController.v63
-rw-r--r--SevSegDisp.v45
-rw-r--r--TEST_Detector.v66
-rw-r--r--TEST_Detector_beh.prj3
-rwxr-xr-xTEST_Detector_isim_beh.exebin0 -> 21792 bytes
-rw-r--r--TEST_Detector_isim_beh.wdbbin0 -> 144 bytes
-rw-r--r--_xmsgs/pn_parser.xmsgs15
-rw-r--r--debouncer.v56
-rw-r--r--detector.wcfg43
-rw-r--r--fuse.log24
-rw-r--r--fuse.xmsgs15
-rw-r--r--fuseRelaunch.cmd1
-rw-r--r--iseconfig/Detector.xreport215
-rw-r--r--iseconfig/lab6.projectmgr58
-rw-r--r--isim.cmd3
-rw-r--r--isim.log37
-rw-r--r--isim/TEST_Detector_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbgbin0 -> 4736 bytes
-rwxr-xr-xisim/TEST_Detector_isim_beh.exe.sim/TEST_Detector_isim_beh.exebin0 -> 16512 bytes
-rw-r--r--isim/TEST_Detector_isim_beh.exe.sim/isimcrash.log0
-rw-r--r--isim/TEST_Detector_isim_beh.exe.sim/isimkernel.log10
-rw-r--r--isim/TEST_Detector_isim_beh.exe.sim/netId.datbin0 -> 84 bytes
-rw-r--r--isim/TEST_Detector_isim_beh.exe.sim/tmp_save/_1bin0 -> 2678 bytes
-rw-r--r--isim/TEST_Detector_isim_beh.exe.sim/work/TEST_Detector_isim_beh.exe_main.c36
-rw-r--r--isim/TEST_Detector_isim_beh.exe.sim/work/TEST_Detector_isim_beh.exe_main.lin64.obin0 -> 2448 bytes
-rw-r--r--isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.c547
-rw-r--r--isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.didatbin0 -> 3112 bytes
-rw-r--r--isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.lin64.obin0 -> 7992 bytes
-rw-r--r--isim/TEST_Detector_isim_beh.exe.sim/work/m_14253225476704866645_1235880303.c286
-rw-r--r--isim/TEST_Detector_isim_beh.exe.sim/work/m_14253225476704866645_1235880303.didatbin0 -> 3440 bytes
-rw-r--r--isim/TEST_Detector_isim_beh.exe.sim/work/m_14253225476704866645_1235880303.lin64.obin0 -> 5176 bytes
-rw-r--r--isim/TEST_Detector_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c337
-rw-r--r--isim/TEST_Detector_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didatbin0 -> 5556 bytes
-rw-r--r--isim/TEST_Detector_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.obin0 -> 5232 bytes
-rw-r--r--isim/isim_usage_statistics.html5
-rw-r--r--isim/lockfile0
-rw-r--r--isim/pn_info1
-rw-r--r--isim/work/@detector.sdbbin0 -> 4098 bytes
-rw-r--r--isim/work/@t@e@s@t_@detector.sdbbin0 -> 3126 bytes
-rw-r--r--isim/work/glbl.sdbbin0 -> 5172 bytes
-rw-r--r--lab6.gise102
-rw-r--r--lab6.xise387
-rw-r--r--xilinxsim.ini1
46 files changed, 2596 insertions, 0 deletions
diff --git a/ClockDivider.v b/ClockDivider.v
new file mode 100644
index 0000000..7ced5a7
--- /dev/null
+++ b/ClockDivider.v
@@ -0,0 +1,47 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 15:24:11 03/16/2012
+// Design Name:
+// Module Name: ClockDivider
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+module ClockDivider(
+ input clk_in,
+ input rst,
+ input [23:0] count,
+ output clk_out
+ );
+
+reg clk_out = 0;
+reg [23:0] c = 0;
+
+always @(posedge clk_in or posedge rst) begin
+ if (rst == 1) begin
+ c = 0;
+ clk_out = 0;
+ end else if (c == count) begin
+ clk_out = ~clk_out;
+ c = 0;
+ end else begin
+ c = c + 24'd1;
+ end
+
+
+end
+
+
+
+endmodule
diff --git a/Detector.v b/Detector.v
new file mode 100644
index 0000000..f1bba2a
--- /dev/null
+++ b/Detector.v
@@ -0,0 +1,66 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 14:38:26 04/05/2012
+// Design Name:
+// Module Name: Detector
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Detector(
+ input inp,
+ input clk,
+ input rst,
+ output result,
+ output [1:0] state
+ );
+
+reg [1:0] state;
+reg [1:0] nextstate;
+reg result;
+
+initial begin
+ state = 0;
+ result = 0;
+end
+
+always @(posedge clk or posedge rst) begin
+ if (rst) begin
+ state <= 0;
+ end else begin
+ state <= nextstate;
+ end
+end
+
+always @(*) begin
+ case (state)
+ 2'b00: nextstate = inp ? 2'b01 : 2'b00;
+ 2'b01: nextstate = inp ? 2'b10 : 2'b00;
+ 2'b10: nextstate = inp ? 2'b11 : 2'b00;
+ 2'b11: nextstate = inp ? 2'b11 : 2'b00;
+ default: nextstate = 2'b00;
+ endcase
+end
+
+always @(state) begin
+ case (state)
+ 2'b00: result = 0;
+ 2'b01: result = 0;
+ 2'b10: result = 0;
+ 2'b11: result = 1;
+ default: result = 0;
+ endcase
+end
+
+endmodule
diff --git a/Detector_summary.html b/Detector_summary.html
new file mode 100644
index 0000000..559c488
--- /dev/null
+++ b/Detector_summary.html
@@ -0,0 +1,79 @@
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Detector Project Status</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>lab6.xise</TD>
+<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
+<TD> No Errors </TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>Detector</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>New</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xc6slx16-3csg324</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
+<TD>&nbsp;</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+
+
+
+
+
+
+
+
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 04/05/2012 - 15:00:11</center>
+</BODY></HTML> \ No newline at end of file
diff --git a/DisplayController.v b/DisplayController.v
new file mode 100644
index 0000000..9e4cc66
--- /dev/null
+++ b/DisplayController.v
@@ -0,0 +1,48 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 16:03:47 03/16/2012
+// Design Name:
+// Module Name: DisplayController
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+module DisplayController(
+ input [3:0] A,
+ input [3:0] B,
+ input clk_in,
+ input rst,
+ output [6:0] result,
+ output [3:0] AN
+ );
+
+reg [3:0] AN;
+reg [6:0] result = 0;
+
+wire [6:0] ssd1;
+wire [6:0] ssd2;
+
+reg prev = 0;
+
+SevSegDisp d1(.A(A), .result(ssd1));
+SevSegDisp d2(.A(B), .result(ssd2));
+
+always @( posedge clk_in ) begin
+ prev <= ~prev;
+ result <= prev ? ssd1 : ssd2;
+ AN <= { ~prev, 2'b11, prev };
+end
+
+
+endmodule
diff --git a/FSMController.v b/FSMController.v
new file mode 100644
index 0000000..65cd70b
--- /dev/null
+++ b/FSMController.v
@@ -0,0 +1,63 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 15:33:05 04/05/2012
+// Design Name:
+// Module Name: FSMController
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+module FSMController(
+ input clk,
+ input btn,
+ input [7:0] pattern,
+ input rst,
+ output [6:0] ssd,
+ output [3:0] an
+ );
+reg [6:0] ssd;
+reg [3:0] an;
+
+reg [2:0] idx;
+
+wire inp;
+wire dbbtn;
+wire dbclk;
+wire dpclk;
+wire res;
+wire [1:0] state;
+wire [6:0] ssdw;
+wire [3:0] anw;
+
+ClockDivider cdiv(.count(100), .rst(rst), .clk_in(clk), .clk_out(dbclk));
+ClockDivider dclk(.count(75000), .rst(rst), .clk_in(clk), .clk_out(dpclk));
+debouncer dbclk(.clk_1M(dbclk), .rst(rst), .din(btn), .dout(dbbtn));
+
+Detector d(.inp(inp), .clk(dbbtn), .rst(rst), .result(res), .state(state));
+
+DisplayController dc(.A({2'b00, state}), .B({3'b000, res}), .rst(rst), .clk_in(dpclk), .result(ssdw), .AN(anw));
+
+initial begin
+ idx = 0;
+end
+
+assign ssd = ssdw;
+assign an = anw;
+
+always @(posedge clk) begin
+ idx = idx + 1;
+ inp <= inp[7-idx];
+end
+
+endmodule
diff --git a/SevSegDisp.v b/SevSegDisp.v
new file mode 100644
index 0000000..8d2c3b1
--- /dev/null
+++ b/SevSegDisp.v
@@ -0,0 +1,45 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 16:01:14 03/16/2012
+// Design Name:
+// Module Name: SevSegDisp
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module SevSegDisp(
+ input [3:0] A,
+ output [6:0] result
+ );
+
+reg [6:0] result = 0;
+
+always @ ( * ) begin
+ case ( A )
+ 4'b0000 : result = 7'b0000001;
+ 4'b0001 : result = 7'b1001111;
+ 4'b0010 : result = 7'b0010010;
+ 4'b0011 : result = 7'b0000110;
+ 4'b0100 : result = 7'b1001100;
+ 4'b0101 : result = 7'b0100100;
+ 4'b0110 : result = 7'b0100000;
+ 4'b0111 : result = 7'b0001111;
+ 4'b1000 : result = 7'b0000000;
+ 4'b1001 : result = 7'b0001100;
+ default : result = 7'b0011010;
+ endcase
+end
+
+endmodule
diff --git a/TEST_Detector.v b/TEST_Detector.v
new file mode 100644
index 0000000..8f038f8
--- /dev/null
+++ b/TEST_Detector.v
@@ -0,0 +1,66 @@
+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 15:01:00 04/05/2012
+// Design Name: Detector
+// Module Name: /home/michael/Documents/School/EC311/lab6/TEST_Detector.v
+// Project Name: lab6
+// Target Device:
+// Tool versions:
+// Description:
+//
+// Verilog Test Fixture created by ISE for module: Detector
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+////////////////////////////////////////////////////////////////////////////////
+
+module TEST_Detector;
+
+ // Inputs
+ reg inp;
+ reg clk;
+ reg rst;
+
+ // Outputs
+ wire result;
+ wire [1:0] state;
+
+ // Instantiate the Unit Under Test (UUT)
+ Detector uut (
+ .inp(inp),
+ .clk(clk),
+ .rst(rst),
+ .result(result),
+ .state(state)
+ );
+
+ reg [19:0] pattern = 20'b11010111011111110110;
+ reg [15:0] i;
+ initial begin
+ // Initialize Inputs
+ inp = 0;
+ clk = 0;
+ rst = 0;
+ i = 0;
+
+ // Wait 100 ns for global reset to finish
+ #50;
+
+ // Add stimulus here
+ for (i = 0; i < 20; i = i + 1) begin
+ inp = pattern[19-i];
+ clk = ~clk; #5;
+ clk = ~clk; #5;
+ end
+ end
+
+endmodule
+
diff --git a/TEST_Detector_beh.prj b/TEST_Detector_beh.prj
new file mode 100644
index 0000000..725319e
--- /dev/null
+++ b/TEST_Detector_beh.prj
@@ -0,0 +1,3 @@
+verilog work "Detector.v"
+verilog work "TEST_Detector.v"
+verilog work "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v"
diff --git a/TEST_Detector_isim_beh.exe b/TEST_Detector_isim_beh.exe
new file mode 100755
index 0000000..beb9ccd
--- /dev/null
+++ b/TEST_Detector_isim_beh.exe
Binary files differ
diff --git a/TEST_Detector_isim_beh.wdb b/TEST_Detector_isim_beh.wdb
new file mode 100644
index 0000000..093e2eb
--- /dev/null
+++ b/TEST_Detector_isim_beh.wdb
Binary files differ
diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs
new file mode 100644
index 0000000..54b96d0
--- /dev/null
+++ b/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated -->
+<!-- by the Xilinx ISE software. Any direct editing or -->
+<!-- changes made to this file may result in unpredictable -->
+<!-- behavior or data corruption. It is strongly advised that -->
+<!-- users do not edit the contents of this file. -->
+<!-- -->
+<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;/home/michael/Documents/School/EC311/lab6/FSMController.v&quot; into library work</arg>
+</msg>
+
+</messages>
+
diff --git a/debouncer.v b/debouncer.v
new file mode 100644
index 0000000..d37cf6d
--- /dev/null
+++ b/debouncer.v
@@ -0,0 +1,56 @@
+module debouncer(clk_1M, rst, din, dout);
+ input clk_1M;
+ input rst;
+ input din;
+ output dout;
+
+ reg dout;
+ reg [21:0] count;
+
+ reg sync0; // first stage of synchronizer
+ reg sync1; // second stage of synchronizer
+
+ reg prev; // register for edge detection
+
+ // synchronize input. (Synchronizers will be discussed in a future lab.)
+ always @(posedge clk_1M or posedge rst) begin
+ if (rst == 1) begin
+ sync0 <= 0;
+ sync1 <= 0;
+ end
+ else begin
+ sync0 <= din;
+ sync1 <= sync0;
+ end
+ end // always
+
+ // perform an edge detect on the synchronized input.
+ always @(posedge clk_1M or posedge rst) begin
+ if (rst == 1) begin
+ prev <= 0;
+ end
+ else begin
+ prev <= sync1;
+ end
+ end // always
+
+ // state machine/counter for timing the debouncing.
+ always @(posedge clk_1M or posedge rst) begin
+ if (rst == 1) begin
+ count <= 0;
+ end
+ else begin
+ if (count == 0) begin
+ if (sync1 == 1 && prev == 0) begin // rising edge detect
+ count <= 22'd100000; // 100,000 us = 100ms delay
+ end
+ dout <= 0;
+ end
+ else begin
+ count <= count - 22'd1;
+ dout <= 1;
+ end
+ end
+ end // always
+
+endmodule
diff --git a/detector.wcfg b/detector.wcfg
new file mode 100644
index 0000000..1310b38
--- /dev/null
+++ b/detector.wcfg
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+ <wave_state>
+ </wave_state>
+ <db_ref_list>
+ <db_ref path="/home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.wdb" id="1" type="auto">
+ <top_modules>
+ <top_module name="TEST_Detector" />
+ <top_module name="glbl" />
+ </top_modules>
+ </db_ref>
+ </db_ref_list>
+ <WVObjectSize size="7" />
+ <wvobject fp_name="/TEST_Detector/result" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">result</obj_property>
+ <obj_property name="ObjectShortName">result</obj_property>
+ </wvobject>
+ <wvobject fp_name="/TEST_Detector/state" type="array" db_ref_id="1">
+ <obj_property name="ElementShortName">state[1:0]</obj_property>
+ <obj_property name="ObjectShortName">state[1:0]</obj_property>
+ </wvobject>
+ <wvobject fp_name="/TEST_Detector/inp" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">inp</obj_property>
+ <obj_property name="ObjectShortName">inp</obj_property>
+ </wvobject>
+ <wvobject fp_name="/TEST_Detector/clk" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">clk</obj_property>
+ <obj_property name="ObjectShortName">clk</obj_property>
+ </wvobject>
+ <wvobject fp_name="/TEST_Detector/rst" type="logic" db_ref_id="1">
+ <obj_property name="ElementShortName">rst</obj_property>
+ <obj_property name="ObjectShortName">rst</obj_property>
+ </wvobject>
+ <wvobject fp_name="/TEST_Detector/pattern" type="array" db_ref_id="1">
+ <obj_property name="ElementShortName">pattern[15:0]</obj_property>
+ <obj_property name="ObjectShortName">pattern[15:0]</obj_property>
+ <obj_property name="Radix">BINARYRADIX</obj_property>
+ </wvobject>
+ <wvobject fp_name="/TEST_Detector/i" type="array" db_ref_id="1">
+ <obj_property name="ElementShortName">i[15:0]</obj_property>
+ <obj_property name="ObjectShortName">i[15:0]</obj_property>
+ </wvobject>
+</wave_config>
diff --git a/fuse.log b/fuse.log
new file mode 100644
index 0000000..44e0298
--- /dev/null
+++ b/fuse.log
@@ -0,0 +1,24 @@
+Running: /home/michael/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "/home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.exe" -prj "/home/michael/Documents/School/EC311/lab6/TEST_Detector_beh.prj" "work.TEST_Detector" "work.glbl"
+ISim O.87xd (signature 0x8ddf5b5d)
+Number of CPUs detected in this system: 2
+Turning on mult-threading, number of parallel sub-compilation jobs: 4
+Determining compilation order of HDL files
+Analyzing Verilog file "/home/michael/Documents/School/EC311/lab6/Detector.v" into library work
+WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab6/Detector.v" Line 29: Redeclaration of ansi port state is not allowed
+WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab6/Detector.v" Line 31: Redeclaration of ansi port result is not allowed
+Analyzing Verilog file "/home/michael/Documents/School/EC311/lab6/TEST_Detector.v" into library work
+Analyzing Verilog file "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" into library work
+Starting static elaboration
+Completed static elaboration
+Fuse Memory Usage: 94996 KB
+Fuse CPU Usage: 1550 ms
+Compiling module Detector
+Compiling module TEST_Detector
+Compiling module glbl
+Time Resolution for simulation is 1ps.
+Waiting for 1 sub-compilation(s) to finish...
+Compiled 3 Verilog Units
+Built simulation executable /home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.exe
+Fuse Memory Usage: 393016 KB
+Fuse CPU Usage: 1580 ms
+GCC CPU Usage: 380 ms
diff --git a/fuse.xmsgs b/fuse.xmsgs
new file mode 100644
index 0000000..cc5dbd1
--- /dev/null
+++ b/fuse.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="HDLCompiler" num="751" delta="unknown" >"/home/michael/Documents/School/EC311/lab6/Detector.v" Line 29: Redeclaration of ansi port <arg fmt="%s" index="1">state</arg> is not allowed
+</msg>
+
+<msg type="warning" file="HDLCompiler" num="751" delta="unknown" >"/home/michael/Documents/School/EC311/lab6/Detector.v" Line 31: Redeclaration of ansi port <arg fmt="%s" index="1">result</arg> is not allowed
+</msg>
+
+</messages>
+
diff --git a/fuseRelaunch.cmd b/fuseRelaunch.cmd
new file mode 100644
index 0000000..f303178
--- /dev/null
+++ b/fuseRelaunch.cmd
@@ -0,0 +1 @@
+-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "/home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.exe" -prj "/home/michael/Documents/School/EC311/lab6/TEST_Detector_beh.prj" "work.TEST_Detector" "work.glbl"
diff --git a/iseconfig/Detector.xreport b/iseconfig/Detector.xreport
new file mode 100644
index 0000000..2f9d918
--- /dev/null
+++ b/iseconfig/Detector.xreport
@@ -0,0 +1,215 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="2.0" >
+ <header>
+ <DateModified>2012-04-05T15:00:11</DateModified>
+ <ModuleName>Detector</ModuleName>
+ <SummaryTimeStamp>Unknown</SummaryTimeStamp>
+ <SavedFilePath>/home/michael/Documents/School/EC311/lab6/iseconfig/Detector.xreport</SavedFilePath>
+ <ImplementationReportsDirectory>/home/michael/Documents/School/EC311/lab6</ImplementationReportsDirectory>
+ <DateInitialized>2012-04-05T15:00:10</DateInitialized>
+ <EnableMessageFiltering>false</EnableMessageFiltering>
+ </header>
+ <body>
+ <viewgroup label="Design Overview" >
+ <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="Detector_summary.html" label="Summary" >
+ <toc-item title="Design Overview" target="Design Overview" />
+ <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+ <toc-item title="Performance Summary" target="Performance Summary" />
+ <toc-item title="Failing Constraints" target="Failing Constraints" />
+ <toc-item title="Detailed Reports" target="Detailed Reports" />
+ </view>
+ <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="Detector_envsettings.html" label="System Settings" />
+ <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="Detector_map.xrpt" label="IOB Properties" />
+ <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="Detector_map.xrpt" label="Control Set Information" />
+ <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="Detector_map.xrpt" label="Module Level Utilization" />
+ <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="Detector.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+ <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="Detector_par.xrpt" label="Pinout Report" />
+ <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="Detector_par.xrpt" label="Clock Report" />
+ <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="Detector.twx" label="Static Timing" />
+ <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="Detector_html/fit/report.htm" label="CPLD Fitter Report" />
+ <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="Detector_html/tim/report.htm" label="CPLD Timing Report" />
+ </viewgroup>
+ <viewgroup label="XPS Errors and Warnings" >
+ <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+ <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+ <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+ </viewgroup>
+ <viewgroup label="XPS Reports" >
+ <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
+ <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
+ <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
+ <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="Detector.log" label="System Log File" />
+ </viewgroup>
+ <viewgroup label="Errors and Warnings" >
+ <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+ <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+ <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+ <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+ <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+ <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+ <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+ <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+ <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+ <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY