1 files changed, 63 insertions, 0 deletions
diff --git a/FSMController.v b/FSMController.v
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index 0000000..65cd70b
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+++ b/FSMController.v
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:33:05 04/05/2012 
+// Design Name: 
+// Module Name:    FSMController 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module FSMController(
+    input clk,
+	 input btn,
+    input [7:0] pattern,
+	 input rst,
+    output [6:0] ssd,
+    output [3:0] an
+    );
+reg [6:0] ssd;
+reg [3:0] an;
+
+reg [2:0] idx;
+
+wire inp;
+wire dbbtn;
+wire dbclk;
+wire dpclk;
+wire res;
+wire [1:0] state;
+wire [6:0] ssdw;
+wire [3:0] anw;
+
+ClockDivider cdiv(.count(100), .rst(rst), .clk_in(clk), .clk_out(dbclk));
+ClockDivider dclk(.count(75000), .rst(rst), .clk_in(clk), .clk_out(dpclk));
+debouncer dbclk(.clk_1M(dbclk), .rst(rst), .din(btn), .dout(dbbtn));
+
+Detector d(.inp(inp), .clk(dbbtn), .rst(rst), .result(res), .state(state));
+
+DisplayController dc(.A({2'b00, state}), .B({3'b000, res}), .rst(rst), .clk_in(dpclk), .result(ssdw), .AN(anw));
+
+initial begin
+	idx = 0;
+end
+
+assign ssd = ssdw;
+assign an = anw;
+
+always @(posedge clk) begin
+	idx = idx + 1;	
+	inp <= inp[7-idx];
+end
+
+endmodule