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diff --git a/TEST_Detector.v b/TEST_Detector.v
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+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   15:01:00 04/05/2012
+// Design Name:   Detector
+// Module Name:   /home/michael/Documents/School/EC311/lab6/TEST_Detector.v
+// Project Name:  lab6
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: Detector
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module TEST_Detector;
+
+	// Inputs
+	reg inp;
+	reg clk;
+	reg rst;
+
+	// Outputs
+	wire result;
+	wire [1:0] state;
+
+	// Instantiate the Unit Under Test (UUT)
+	Detector uut (
+		.inp(inp), 
+		.clk(clk), 
+		.rst(rst), 
+		.result(result), 
+		.state(state)
+	);
+	
+	reg [19:0] pattern = 20'b11010111011111110110;
+	reg [15:0] i;
+	initial begin
+		// Initialize Inputs
+		inp = 0;
+		clk = 0;
+		rst = 0;
+		i = 0;
+
+		// Wait 100 ns for global reset to finish
+		#50;
+        
+		// Add stimulus here
+		for (i = 0; i < 20; i = i + 1) begin
+			inp = pattern[19-i];
+			clk = ~clk; #5;
+			clk = ~clk; #5;
+		end
+	end
+      
+endmodule
+