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author | Michael Abed <michaelabed@gmail.com> | 2012-12-02 12:11:54 -0500 |
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committer | Michael Abed <michaelabed@gmail.com> | 2012-12-02 12:11:54 -0500 |
commit | a93f8d8f6331f28b8862258db95cea3ac14f7787 (patch) | |
tree | f624b9f481b06157c7d1041300703130546ea8cb /adder_64bit_csel.v | |
download | ec413-lab3-master.tar.gz ec413-lab3-master.tar.bz2 ec413-lab3-master.zip |
Diffstat (limited to 'adder_64bit_csel.v')
-rwxr-xr-x | adder_64bit_csel.v | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/adder_64bit_csel.v b/adder_64bit_csel.v new file mode 100755 index 0000000..4c7ebb7 --- /dev/null +++ b/adder_64bit_csel.v @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:50:17 09/26/2012 +// Design Name: +// Module Name: adder_64bit_csel +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module adder_64bit_csel( + input [63:0] A, + input [63:0] B, + input Carry_In, + output [63:0] Sum, + output Carry_Out + ); + +wire c1, c2, c3; + +wire [31:0] o1, o2; // possible outputs for higher bits + +adder_32bit a1(.Carry_Out(c1), .Sum(Sum[31:0]), .A(A[31:0]), .B(B[31:0]), .Carry_In(Carry_In)); + +adder_32bit a2(.Carry_Out(c2), .Sum(o1), .A(A[63:32]), .B(B[63:32]), .Carry_In(1'b0)); +adder_32bit a3(.Carry_Out(c3), .Sum(o2), .A(A[63:32]), .B(B[63:32]), .Carry_In(1'b1)); + +mux2_32bit m1(.a(o2), .b(o1), .sel(c1), .o(Sum[63:32])); +mux2_1bit m2(.a(c3), .b(c2), .sel(c1), .o(Carry_Out)); + +endmodule |