add verilog codeHEADmaster

1 files changed, 31 insertions, 0 deletions

diff --git a/csel.v b/csel.v
new file mode 100755
index 0000000..d1b29d7
--- /dev/null
+++ b/csel.v
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    20:27:50 09/27/2012 
+// Design Name: 
+// Module Name:    csel 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module csel(
+    input c_prev,
+    input c0,
+    input c1,
+    output sel
+    );
+wire i1;
+
+and #1 a1(i1, c_prev, c1);
+or #1 o1(sel, c0, i1);
+endmodule