1 files changed, 27 insertions, 0 deletions
diff --git a/verilog/DFF.v b/verilog/DFF.v
new file mode 100755
index 0000000..53ae504
--- /dev/null
+++ b/verilog/DFF.v
@@ -0,0 +1,27 @@
+//D Flip-flop
+module DFF(D,     // DFF Input
+           Q,     // DFF Output
+			  Write, // Only accept input when this is set
+			  Reset, // Synchronous Reset
+			  Clk);  // Clock
+
+	//-------------Input Ports-----------------------------
+	input D;
+	input Write;
+	input Reset;
+	input Clk;
+	//-------------Output Ports----------------------------
+	output Q;
+	//-------------Wires-----------------------------------
+	//-------------Other-----------------------------------
+	reg data;
+	//------------Code Starts Here-------------------------
+	assign Q= data;
+	always @ (posedge Clk)
+	if (Reset) begin
+		data <= 1'b0;
+	end  else begin
+		if(Write)
+			data <= D; 
+	end
+endmodule