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author | Michael Abed <michaelabed@gmail.com> | 2012-12-02 12:13:10 -0500 |
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committer | Michael Abed <michaelabed@gmail.com> | 2012-12-02 12:13:10 -0500 |
commit | e64c18d0e30c33fe4609c881620fa937da7b8ce3 (patch) | |
tree | 1caab3c1934a97fbff1faef1076e34f06c994a6c /verilog/DFF.v | |
download | ec413-lab5-master.tar.gz ec413-lab5-master.tar.bz2 ec413-lab5-master.zip |
Diffstat (limited to 'verilog/DFF.v')
-rwxr-xr-x | verilog/DFF.v | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/verilog/DFF.v b/verilog/DFF.v new file mode 100755 index 0000000..53ae504 --- /dev/null +++ b/verilog/DFF.v @@ -0,0 +1,27 @@ +//D Flip-flop
+module DFF(D, // DFF Input + Q, // DFF Output + Write, // Only accept input when this is set + Reset, // Synchronous Reset + Clk); // Clock
+ + //-------------Input Ports-----------------------------
+ input D; + input Write;
+ input Reset; + input Clk; + //-------------Output Ports---------------------------- + output Q;
+ //-------------Wires----------------------------------- + //-------------Other----------------------------------- + reg data; + //------------Code Starts Here------------------------- + assign Q= data; + always @ (posedge Clk) + if (Reset) begin + data <= 1'b0; + end else begin + if(Write) + data <= D; + end
+endmodule
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