make it workHEADmaster

5 files changed, 24 insertions, 24 deletions

diff --git a/_xmsgs/bitgen.xmsgs b/_xmsgs/bitgen.xmsgs
index 78d5ffb..6581d17 100755
--- a/_xmsgs/bitgen.xmsgs
+++ b/_xmsgs/bitgen.xmsgs
@@ -5,7 +5,7 @@
      behavior or data corruption.  It is strongly advised that

      users do not edit the contents of this file. -->

 <messages>
-<msg type="info" file="Bitgen" num="278" delta="new" >Setting the Persist option to &quot;Yes&quot; with the CONFIG_MODE constraint value &quot;<arg fmt="%s" index="1">UnSpecified</arg>&quot; will result in the 8-bit SelectMap port being persisted.

+<msg type="info" file="Bitgen" num="278" delta="old" >Setting the Persist option to &quot;Yes&quot; with the CONFIG_MODE constraint value &quot;<arg fmt="%s" index="1">UnSpecified</arg>&quot; will result in the 8-bit SelectMap port being persisted.

 </msg>

 
 </messages>
diff --git a/_xmsgs/map.xmsgs b/_xmsgs/map.xmsgs
index b32095a..4ecf2a7 100755
--- a/_xmsgs/map.xmsgs
+++ b/_xmsgs/map.xmsgs
@@ -5,22 +5,22 @@
      behavior or data corruption.  It is strongly advised that

      users do not edit the contents of this file. -->

 <messages>
-<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.

+<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.

 </msg>

 
-<msg type="info" file="LIT" num="244" delta="new" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.

+<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.

 </msg>

 
-<msg type="info" file="Pack" num="1716" delta="new" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)

+<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)

 </msg>

 
-<msg type="info" file="Pack" num="1720" delta="new" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)

+<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)

 </msg>

 
-<msg type="info" file="Map" num="215" delta="new" >The Interim Design Summary has been generated in the MAP Report (.mrp).

+<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).

 </msg>

 
-<msg type="info" file="Pack" num="1650" delta="new" >Map created a placed design.

+<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.

 </msg>

 
 </messages>
diff --git a/_xmsgs/par.xmsgs b/_xmsgs/par.xmsgs
index 848b12c..5f1f5f1 100755
--- a/_xmsgs/par.xmsgs
+++ b/_xmsgs/par.xmsgs
@@ -5,10 +5,10 @@
      behavior or data corruption.  It is strongly advised that

      users do not edit the contents of this file. -->

 <messages>
-<msg type="info" file="Par" num="282" delta="new" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;.  For best performance, set the effort level to &quot;high&quot;.

+<msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;.  For best performance, set the effort level to &quot;high&quot;.

 </msg>

 
-<msg type="info" file="Par" num="459" delta="new" >The Clock Report is not displayed in the non timing-driven mode.

+<msg type="info" file="Par" num="459" delta="old" >The Clock Report is not displayed in the non timing-driven mode.

 </msg>

 
 </messages>
diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs
index 2211003..ee464b0 100755
--- a/_xmsgs/pn_parser.xmsgs
+++ b/_xmsgs/pn_parser.xmsgs
@@ -1,12 +1,12 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- IMPORTANT: This is an internal file that has been generated   -->
-<!--     by the Xilinx ISE software.  Any direct editing or        -->
-<!--     changes made to this file may result in unpredictable     -->
-<!--     behavior or data corruption.  It is strongly advised that -->
-<!--     users do not edit the contents of this file.              -->
-<!--                                                               -->
-<!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.    -->
-
-<messages>
-</messages>
-
+<?xml version="1.0" encoding="UTF-8"?>

+<!-- IMPORTANT: This is an internal file that has been generated   -->

+<!--     by the Xilinx ISE software.  Any direct editing or        -->

+<!--     changes made to this file may result in unpredictable     -->

+<!--     behavior or data corruption.  It is strongly advised that -->

+<!--     users do not edit the contents of this file.              -->

+<!--                                                               -->

+<!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.    -->

+

+<messages>

+</messages>

+

diff --git a/_xmsgs/trce.xmsgs b/_xmsgs/trce.xmsgs
index 120dfa1..80cb2e4 100755
--- a/_xmsgs/trce.xmsgs
+++ b/_xmsgs/trce.xmsgs
@@ -5,11 +5,11 @@
      behavior or data corruption.  It is strongly advised that

      users do not edit the contents of this file. -->

 <messages>
-<msg type="info" file="Timing" num="2698" delta="new" >No timing constraints found, doing default enumeration.</msg>

+<msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg>

 
-<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>

+<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>

 
-<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>

+<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>

 
 </messages>