diff options
| author | Michael Abed <michaelabed@gmail.com> | 2012-02-17 12:08:05 -0500 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-02-17 12:08:05 -0500 |
| commit | 70b77304f37d9681aa3bfa0eb57df0bcfd1aef81 (patch) | |
| tree | 48ab397b4072275dbc5a6b2f92a54d3c79e1fdea /webtalk_pn.xml | |
| parent | 57738e75e221fe61a8f87270b430c0f1c0b8ead5 (diff) | |
| download | ec311-lab1-master.tar.gz ec311-lab1-master.tar.bz2 ec311-lab1-master.zip | |
Diffstat (limited to 'webtalk_pn.xml')
| -rwxr-xr-x | webtalk_pn.xml | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/webtalk_pn.xml b/webtalk_pn.xml index 5409eba..78fb8e5 100755 --- a/webtalk_pn.xml +++ b/webtalk_pn.xml @@ -3,11 +3,11 @@ <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pn" timeStamp="Wed Feb 15 15:16:03 2012">
+<application name="pn" timeStamp="Thu Feb 16 19:53:06 2012">
<section name="Project Information" visible="false">
<property name="ProjectID" value="23EF1CF2DA254B0F8463C6B682ABB1F9" type="project"/>
-<property name="ProjectIteration" value="1" type="project"/>
-<property name="ProjectFile" value="X:/My Documents/ec311/lab1/lab1.xise" type="project"/>
+<property name="ProjectIteration" value="11" type="project"/>
+<property name="ProjectFile" value="X:/My Documents/ec311/ec311-lab1/lab1.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2012-02-15T14:51:10" type="project"/>
</section>
<section name="Project Statistics" visible="true">
@@ -16,6 +16,7 @@ This means code written to parse this file will need to be revisited each subseq <property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
+<property name="PROP_OverwriteSym" value="true" type="process"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
@@ -24,7 +25,7 @@ This means code written to parse this file will need to be revisited each subseq <property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2012-02-15T14:51:10" type="design"/>
<property name="PROP_intWbtProjectID" value="23EF1CF2DA254B0F8463C6B682ABB1F9" type="design"/>
-<property name="PROP_intWbtProjectIteration" value="1" type="process"/>
+<property name="PROP_intWbtProjectIteration" value="11" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
|