diff options
| author | Michael Abed <michaelabed@gmail.com> | 2012-02-17 12:10:31 -0500 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-02-17 12:10:31 -0500 |
| commit | 59d89428d6160fb672c2b6a41339505cc69344d0 (patch) | |
| tree | a774e809a31fc7eae7b0fd0777714c86ffedc9d6 /pa.fromHdl.tcl | |
| parent | 0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a (diff) | |
| download | ec311-lab2-master.tar.gz ec311-lab2-master.tar.bz2 ec311-lab2-master.zip | |
Diffstat (limited to 'pa.fromHdl.tcl')
| -rwxr-xr-x | pa.fromHdl.tcl | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/pa.fromHdl.tcl b/pa.fromHdl.tcl index 2112f38..73123ec 100755 --- a/pa.fromHdl.tcl +++ b/pa.fromHdl.tcl @@ -1,19 +1,19 @@ - -# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator - -create_project -name lab2 -dir "/home/michael/Documents/School/EC311/lab2/planAhead_run_2" -part xc6slx16csg324-3 -set_param project.pinAheadLayout yes -set srcset [get_property srcset [current_run -impl]] -set_property target_constrs_file "ALUSHOW.ucf" [current_fileset -constrset] -set hdlfile [add_files [list {sev_seg_disp.vf}]] -set_property file_type Verilog $hdlfile -set_property library work $hdlfile -set hdlfile [add_files [list {ALU.v}]] -set_property file_type Verilog $hdlfile -set_property library work $hdlfile -set hdlfile [add_files [list {ALUSHOW.vf}]] -set_property file_type Verilog $hdlfile -set_property library work $hdlfile -set_property top ALUSHOW $srcset -add_files [list {ALUSHOW.ucf}] -fileset [get_property constrset [current_run]] -open_rtl_design -part xc6slx16csg324-3 +
+# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator
+
+create_project -name lab2 -dir "X:/My Documents/ec311/ec311-lab2/planAhead_run_2" -part xc6slx16csg324-3
+set_param project.pinAheadLayout yes
+set srcset [get_property srcset [current_run -impl]]
+set_property top ALUSHOW $srcset
+set_property target_constrs_file "ALUSHOW.ucf" [current_fileset -constrset]
+set hdlfile [add_files [list {sev_seg_disp.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {ALU.v}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+set hdlfile [add_files [list {ALUSHOW.vf}]]
+set_property file_type Verilog $hdlfile
+set_property library work $hdlfile
+add_files [list {ALUSHOW.ucf}] -fileset [get_property constrset [current_run]]
+open_rtl_design -part xc6slx16csg324-3
|