diff options
| author | Michael Abed <michaelabed@gmail.com> | 2012-03-29 16:17:45 -0400 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-03-29 16:17:45 -0400 |
| commit | 9540811daaffad7811475ea584333ab633ba8508 (patch) | |
| tree | 9c20071e05b1225f9b466dede6236a7cd53ea851 | |
| parent | f9328ba21afde12326c04e59eb542446faf5fae4 (diff) | |
| download | ec311-lab5-master.tar.gz ec311-lab5-master.tar.bz2 ec311-lab5-master.zip | |
87 files changed, 3818 insertions, 73 deletions
diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..d40292e --- /dev/null +++ b/.gitignore @@ -0,0 +1,3 @@ + +*.un~ + diff --git a/DisplayController.v b/DisplayController.v index 6da8227..8d9a77a 100644 --- a/DisplayController.v +++ b/DisplayController.v @@ -36,7 +36,7 @@ reg [3:0] AN; wire clkdiv; reg [1:0] w = 2'd0; -ClockDivider cdiv(.clk_out(clkdiv), .rst(rst), .clk_in(clk), .count(500_000)); +ClockDivider cdiv(.clk_out(clkdiv), .rst(rst), .clk_in(clk), .count(10)); wire [6:0] o1, o2, o3, o4; diff --git a/DisplayController_summary.html b/DisplayController_summary.html index e3bd536..5983289 100644 --- a/DisplayController_summary.html +++ b/DisplayController_summary.html @@ -7,11 +7,11 @@ <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> <TD>lab5.xise</TD> <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> -<TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab5/_xmsgs/pn_parser.xmsgs?&DataKey=Error'>1 Error</A></TD> +<TD> No Errors </TD> </TR> <TR ALIGN=LEFT> <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> -<TD>DisplayController</TD> +<TD>FIRController</TD> <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> <TD>New</TD> </TR> @@ -75,5 +75,5 @@ </TABLE> -<br><center><b>Date Generated:</b> 03/27/2012 - 16:53:37</center> +<br><center><b>Date Generated:</b> 03/29/2012 - 15:16:18</center> </BODY></HTML>
\ No newline at end of file diff --git a/FIRFilter.v b/FIRFilter.v index dada832..61c0ef8 100644 --- a/FIRFilter.v +++ b/FIRFilter.v @@ -27,16 +27,24 @@ module FIRFilter( reg [15:0] yout; -reg [15:0] yold1; -reg [15:0] yold2; +reg [15:0] yold1=0; +reg [15:0] yold2=0; -always @(*) begin - yout = 20*yin + 15*yold1 + 10*yold2; +always @(yin, yold1, yold2, rst) begin + if (rst) + yout = 0; + else + yout = 20*yin + 15*yold1 + 10*yold2; end -always @(load) begin - yold2 = yold1; - yold1 = yin; +always @(posedge load, posedge rst) begin + if (rst) begin + yold1 = 0; + yold2 = 0; + end else begin + yold2 = yold1; + yold1 = yin; + end end endmodule diff --git a/TEST_Bin2BCD.v b/TEST_Bin2BCD.v new file mode 100644 index 0000000..7561bf6 --- /dev/null +++ b/TEST_Bin2BCD.v @@ -0,0 +1,60 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:26:38 03/29/2012 +// Design Name: Bin2BCD +// Module Name: /home/michael/Documents/School/EC311/lab5/TEST_Bin2BCD.v +// Project Name: lab5 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: Bin2BCD +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_Bin2BCD; + + // Inputs + reg [15:0] bin; + + // Outputs + wire [3:0] one; + wire [3:0] ten; + wire [3:0] hun; + wire [3:0] thous; + + // Instantiate the Unit Under Test (UUT) + Bin2BCD uut ( + .bin(bin), + .one(one), + .ten(ten), + .hun(hun), + .thous(thous) + ); + + initial begin + // Initialize Inputs + bin = 0; + + // Wait 100 ns for global reset to finish + #100; + bin = 7; #50; + bin = 16;#50; + bin = 217;#50; + bin = 1839; #50; + // Add stimulus here + + end + +endmodule + diff --git a/TEST_Bin2BCD_isim_beh.exe b/TEST_Bin2BCD_isim_beh.exe Binary files differnew file mode 100755 index 0000000..beb9ccd --- /dev/null +++ b/TEST_Bin2BCD_isim_beh.exe diff --git a/TEST_DisplayController.v b/TEST_DisplayController.v new file mode 100644 index 0000000..c2c7271 --- /dev/null +++ b/TEST_DisplayController.v @@ -0,0 +1,74 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:17:59 03/29/2012 +// Design Name: DisplayController +// Module Name: /home/michael/Documents/School/EC311/lab5/TEST_DisplayController.v +// Project Name: lab5 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: DisplayController +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_DisplayController; + + // Inputs + reg [3:0] A; + reg [3:0] B; + reg [3:0] C; + reg [3:0] D; + reg clk; + reg rst; + + // Outputs + wire [6:0] ssd; + wire [3:0] AN; + + // Instantiate the Unit Under Test (UUT) + DisplayController uut ( + .A(A), + .B(B), + .C(C), + .D(D), + .clk(clk), + .rst(rst), + .ssd(ssd), + .AN(AN) + ); + + initial begin + // Initialize Inputs + A = 0; + B = 0; + C = 0; + D = 0; + clk = 0; + rst = 0; + + // Wait 100 ns for global reset to finish + #100; + A=4'd3; + B=4'd0; + C=4'd7; + D=4'd9; + while (1) begin + clk = ~clk; #1; + end + // Add stimulus here + + end + +endmodule + diff --git a/TEST_DisplayController_isim_beh.exe b/TEST_DisplayController_isim_beh.exe Binary files differnew file mode 100755 index 0000000..beb9ccd --- /dev/null +++ b/TEST_DisplayController_isim_beh.exe diff --git a/TEST_FirFilter.v b/TEST_FirFilter.v new file mode 100644 index 0000000..fd8454a --- /dev/null +++ b/TEST_FirFilter.v @@ -0,0 +1,60 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:29:29 03/29/2012 +// Design Name: FIRFilter +// Module Name: /home/michael/Documents/School/EC311/lab5/TEST_FirFilter.v +// Project Name: lab5 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: FIRFilter +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_FirFilter; + + // Inputs + reg [7:0] yin; + reg load; + reg rst; + + // Outputs + wire [15:0] yout; + + // Instantiate the Unit Under Test (UUT) + FIRFilter uut ( + .yin(yin), + .yout(yout), + .load(load), + .rst(rst) + ); + + initial begin + // Initialize Inputs + yin = 0; + load = 0; + rst = 0; + + // Wait 100 ns for global reset to finish + #100; + + // Add stimulus here + yin = 100; #10; load = 1; #10 load = 0; #10; + yin = 12; #10; load = 1; #10 load = 0; #10; + yin = 157; #10; load = 1; #10 load = 0; #10; + yin = 56; #10; load = 1; #10 load = 0; #10; + end + +endmodule + diff --git a/TEST_FirFilter_beh.prj b/TEST_FirFilter_beh.prj new file mode 100644 index 0000000..ef59f44 --- /dev/null +++ b/TEST_FirFilter_beh.prj @@ -0,0 +1,3 @@ +verilog work "FIRFilter.v" +verilog work "TEST_FirFilter.v" +verilog work "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" diff --git a/TEST_FirFilter_isim_beh.exe b/TEST_FirFilter_isim_beh.exe Binary files differnew file mode 100755 index 0000000..beb9ccd --- /dev/null +++ b/TEST_FirFilter_isim_beh.exe diff --git a/TEST_FirFilter_isim_beh.wdb b/TEST_FirFilter_isim_beh.wdb Binary files differnew file mode 100644 index 0000000..5755f5a --- /dev/null +++ b/TEST_FirFilter_isim_beh.wdb diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs index 278dafe..4c3d12b 100644 --- a/_xmsgs/pn_parser.xmsgs +++ b/_xmsgs/pn_parser.xmsgs @@ -8,7 +8,7 @@ <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> <messages> -<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/michael/Documents/School/EC311/lab5/DisplayController.v" into library work</arg> +<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/michael/Documents/School/EC311/lab5/FIRFilter.v" into library work</arg> </msg> </messages> diff --git a/firfilter.wcfg b/firfilter.wcfg new file mode 100644 index 0000000..0facbc5 --- /dev/null +++ b/firfilter.wcfg @@ -0,0 +1,38 @@ +<?xml version="1.0" encoding="UTF-8"?> +<wave_config> + <wave_state> + </wave_state> + <db_ref_list> + <db_ref path="/home/michael/Documents/School/EC311/lab5/TEST_FirFilter_isim_beh.wdb" id="1" type="auto"> + <top_modules> + <top_module name="TEST_FirFilter" /> + <top_module name="glbl" /> + </top_modules> + </db_ref> + </db_ref_list> + <WVObjectSize size="6" /> + <wvobject fp_name="/TEST_FirFilter/yout" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">yout[15:0]</obj_property> + <obj_property name="ObjectShortName">yout[15:0]</obj_property> + </wvobject> + <wvobject fp_name="/TEST_FirFilter/yin" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">yin[7:0]</obj_property> + <obj_property name="ObjectShortName">yin[7:0]</obj_property> + </wvobject> + <wvobject fp_name="/TEST_FirFilter/load" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">load</obj_property> + <obj_property name="ObjectShortName">load</obj_property> + </wvobject> + <wvobject fp_name="/TEST_FirFilter/rst" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">rst</obj_property> + <obj_property name="ObjectShortName">rst</obj_property> + </wvobject> + <wvobject fp_name="/TEST_FirFilter/uut/yold1" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">yold1[15:0]</obj_property> + <obj_property name="ObjectShortName">yold1[15:0]</obj_property> + </wvobject> + <wvobject fp_name="/TEST_FirFilter/uut/yold2" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">yold2[15:0]</obj_property> + <obj_property name="ObjectShortName">yold2[15:0]</obj_property> + </wvobject> +</wave_config> diff --git a/fuse.log b/fuse.log new file mode 100644 index 0000000..cfaf0da --- /dev/null +++ b/fuse.log @@ -0,0 +1,23 @@ +Running: /home/michael/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "/home/michael/Documents/School/EC311/lab5/TEST_FirFilter_isim_beh.exe" -prj "/home/michael/Documents/School/EC311/lab5/TEST_FirFilter_beh.prj" "work.TEST_FirFilter" "work.glbl" +ISim O.87xd (signature 0x8ddf5b5d) +Number of CPUs detected in this system: 2 +Turning on mult-threading, number of parallel sub-compilation jobs: 4 +Determining compilation order of HDL files +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab5/FIRFilter.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab5/FIRFilter.v" Line 28: Redeclaration of ansi port yout is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab5/TEST_FirFilter.v" into library work +Analyzing Verilog file "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" into library work +Starting static elaboration +Completed static elaboration +Fuse Memory Usage: 94996 KB +Fuse CPU Usage: 1620 ms +Compiling module FIRFilter +Compiling module TEST_FirFilter +Compiling module glbl +Time Resolution for simulation is 1ps. +Waiting for 1 sub-compilation(s) to finish... +Compiled 3 Verilog Units +Built simulation executable /home/michael/Documents/School/EC311/lab5/TEST_FirFilter_isim_beh.exe +Fuse Memory Usage: 393012 KB +Fuse CPU Usage: 1640 ms +GCC CPU Usage: 300 ms diff --git a/fuse.xmsgs b/fuse.xmsgs new file mode 100644 index 0000000..ec4f168 --- /dev/null +++ b/fuse.xmsgs @@ -0,0 +1,12 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated + by the Xilinx ISE software. Any direct editing or + changes made to this file may result in unpredictable + behavior or data corruption. It is strongly advised that + users do not edit the contents of this file. --> +<messages> +<msg type="warning" file="HDLCompiler" num="751" delta="unknown" >"/home/michael/Documents/School/EC311/lab5/FIRFilter.v" Line 28: Redeclaration of ansi port <arg fmt="%s" index="1">yout</arg> is not allowed +</msg> + +</messages> + diff --git a/fuseRelaunch.cmd b/fuseRelaunch.cmd new file mode 100644 index 0000000..8390901 --- /dev/null +++ b/fuseRelaunch.cmd @@ -0,0 +1 @@ +-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "/home/michael/Documents/School/EC311/lab5/TEST_FirFilter_isim_beh.exe" -prj "/home/michael/Documents/School/EC311/lab5/TEST_FirFilter_beh.prj" "work.TEST_FirFilter" "work.glbl" diff --git a/iseconfig/FIRController.xreport b/iseconfig/FIRController.xreport index 80763e1..70ab327 100644 --- a/iseconfig/FIRController.xreport +++ b/iseconfig/FIRController.xreport @@ -1,11 +1,11 @@ <?xml version='1.0' encoding='UTF-8'?> <report-views version="2.0" > <header> - <DateModified>2012-03-27T16:33:33</DateModified> - <ModuleName>DisplayController</ModuleName> + <DateModified>2012-03-29T15:16:18</DateModified> + <ModuleName>FIRController</ModuleName> <SummaryTimeStamp>Unknown</SummaryTimeStamp> <SavedFilePath>/home/michael/Documents/School/EC311/lab5/iseconfig/FIRController.xreport</SavedFilePath> - <ImplementationReportsDirectory>/home/michael/Documents/School/EC311/lab5</ImplementationReportsDirectory> + <ImplementationReportsDirectory>/home/michael/Documents/School/EC311/lab5/</ImplementationReportsDirectory> <DateInitialized>2012-03-27T16:33:33</DateInitialized> <EnableMessageFiltering>false</EnableMessageFiltering> </header> diff --git a/iseconfig/lab5.projectmgr b/iseconfig/lab5.projectmgr index ce403c0..5788bca 100644 --- a/iseconfig/lab5.projectmgr +++ b/iseconfig/lab5.projectmgr @@ -1,4 +1,4 @@ -<?xml version="1.0" encoding="utf-8"?> +<?xml version='1.0' encoding='utf-8'?> <!--This is an ISE project configuration file.--> <!--It holds project specific layout data for the projectmgr plugin.--> <!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.--> @@ -9,13 +9,13 @@ <ClosedNodesVersion>2</ClosedNodesVersion> </ClosedNodes> <SelectedItems> - <SelectedItem>dc - DisplayController (/home/michael/Documents/School/EC311/lab5/DisplayController.v)</SelectedItem> + <SelectedItem>ff - FIRFilter (/home/michael/Documents/School/EC311/lab5/FIRFilter.v)</SelectedItem> </SelectedItems> - <ScrollbarPosition orientation="vertical" >1</ScrollbarPosition> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000155000000020000000000000000000000000200000064ffffffff000000810000000300000002000001550000000100000003000000000000000100000003</ViewHeaderState> <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> - <CurrentItem>dc - DisplayController (/home/michael/Documents/School/EC311/lab5/DisplayController.v)</CurrentItem> + <CurrentItem>ff - FIRFilter (/home/michael/Documents/School/EC311/lab5/FIRFilter.v)</CurrentItem> </ItemView> <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" > <ClosedNodes> @@ -23,13 +23,13 @@ <ClosedNode>Design Utilities</ClosedNode> </ClosedNodes> <SelectedItems> - <SelectedItem></SelectedItem> + <SelectedItem/> </SelectedItems> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000154000000010000000100000000000000000000000064ffffffff000000810000000000000001000001540000000100000000</ViewHeaderState> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> - <CurrentItem></CurrentItem> + <CurrentItem/> </ItemView> <ItemView guiview="File" > <ClosedNodes> @@ -73,5 +73,49 @@ <CurrentItem></CurrentItem> </ItemView> <SourceProcessView>000000ff00000000000000020000013f0000012001000000060100000002</SourceProcessView> - <CurrentView>Implementation</CurrentView> + <CurrentView>Behavioral Simulation</CurrentView> + <ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" > + <ClosedNodes> + <ClosedNodesVersion>2</ClosedNodesVersion> + <ClosedNode>/FIRController |home|michael|Documents|School|EC311|lab5|FIRController.v/dc - DisplayController</ClosedNode> + <ClosedNode>/TEST_Bin2BCD |home|michael|Documents|School|EC311|lab5|TEST_Bin2BCD.v</ClosedNode> + <ClosedNode>/TEST_DisplayController |home|michael|Documents|School|EC311|lab5|TEST_DisplayController.v</ClosedNode> + <ClosedNode>/TEST_FirFilter |home|michael|Documents|School|EC311|lab5|TEST_FirFilter.v</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem>TEST_FirFilter (/home/michael/Documents/School/EC311/lab5/TEST_FirFilter.v)</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000016e000000020000000000000000000000000200000064ffffffff0000008100000003000000020000016e0000000100000003000000000000000100000003</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>TEST_FirFilter (/home/michael/Documents/School/EC311/lab5/TEST_FirFilter.v)</CurrentItem> + </ItemView> + <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>Design Utilities</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem></SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000154000000010000000100000000000000000000000064ffffffff000000810000000000000001000001540000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem></CurrentItem> + </ItemView> + <ItemView engineview="BehavioralSim" sourcetype="DESUT_VERILOG" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem></SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000154000000010000000100000000000000000000000064ffffffff000000810000000000000001000001540000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem></CurrentItem> + </ItemView> </Project> diff --git a/isim.cmd b/isim.cmd new file mode 100644 index 0000000..fff18e8 --- /dev/null +++ b/isim.cmd @@ -0,0 +1,3 @@ +onerror {resume} +wave add / +run 1000 ns; diff --git a/isim.log b/isim.log new file mode 100644 index 0000000..5611dad --- /dev/null +++ b/isim.log @@ -0,0 +1,38 @@ +ISim log file +Running: /home/michael/Documents/School/EC311/lab5/TEST_FirFilter_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/michael/Documents/School/EC311/lab5/TEST_FirFilter_isim_beh.wdb +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +Time resolution is 1 ps +# onerror resume +# wave add / +# run 1000 ns +Simulator is doing circuit initialization process. +Finished circuit initialization process. +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +Finished circuit initialization process. +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +Finished circuit initialization process. +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +Finished circuit initialization process. +# exit 0 diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg b/isim/TEST_Bin2BCD_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg Binary files differnew file mode 100644 index 0000000..e4626e0 --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/TEST_Bin2BCD_isim_beh.exe b/isim/TEST_Bin2BCD_isim_beh.exe.sim/TEST_Bin2BCD_isim_beh.exe Binary files differnew file mode 100755 index 0000000..fa04231 --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/TEST_Bin2BCD_isim_beh.exe diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/isimcrash.log b/isim/TEST_Bin2BCD_isim_beh.exe.sim/isimcrash.log new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/isimcrash.log diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/isimkernel.log b/isim/TEST_Bin2BCD_isim_beh.exe.sim/isimkernel.log new file mode 100644 index 0000000..04dde27 --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/isimkernel.log @@ -0,0 +1,29 @@ +Command line: + TEST_Bin2BCD_isim_beh.exe + -simmode gui + -simrunnum 0 + -socket 36066 + +Thu Mar 29 15:27:41 2012 + + + Elaboration Time: 0.02 sec + + Current Memory Usage: 181.277 Meg + + Total Signals : 18 + Total Nets : 45 + Total Signal Drivers : 10 + Total Blocks : 3 + Total Primitive Blocks : 2 + Total Processes : 13 + Total Traceable Variables : 25 + Total Scalar Nets and Variables : 193 +Total Line Count : 39 + + Total Simulation Time: 0.04 sec + + Current Memory Usage: 256.778 Meg + +Thu Mar 29 15:28:03 2012 + diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/netId.dat b/isim/TEST_Bin2BCD_isim_beh.exe.sim/netId.dat Binary files differnew file mode 100644 index 0000000..9ecf9af --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/netId.dat diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/tmp_save/_1 b/isim/TEST_Bin2BCD_isim_beh.exe.sim/tmp_save/_1 Binary files differnew file mode 100644 index 0000000..def0567 --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/tmp_save/_1 diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/TEST_Bin2BCD_isim_beh.exe_main.c b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/TEST_Bin2BCD_isim_beh.exe_main.c new file mode 100644 index 0000000..e214f38 --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/TEST_Bin2BCD_isim_beh.exe_main.c @@ -0,0 +1,36 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +#include "xsi.h" + +struct XSI_INFO xsi_info; + + + +int main(int argc, char **argv) +{ + xsi_init_design(argc, argv); + xsi_register_info(&xsi_info); + + xsi_register_min_prec_unit(-12); + work_m_16012083836245549588_2618506667_init(); + work_m_17956504886923659924_0893867553_init(); + work_m_16541823861846354283_2073120511_init(); + + + xsi_register_tops("work_m_17956504886923659924_0893867553"); + xsi_register_tops("work_m_16541823861846354283_2073120511"); + + + return xsi_run_simulation(argc, argv); + +} diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/TEST_Bin2BCD_isim_beh.exe_main.lin64.o b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/TEST_Bin2BCD_isim_beh.exe_main.lin64.o Binary files differnew file mode 100644 index 0000000..901350c --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/TEST_Bin2BCD_isim_beh.exe_main.lin64.o diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16012083836245549588_2618506667.c b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16012083836245549588_2618506667.c new file mode 100644 index 0000000..d490288 --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16012083836245549588_2618506667.c @@ -0,0 +1,707 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab5/Bin2BCD.v"; +static int ng1[] = {0, 0}; +static int ng2[] = {15, 0}; +static int ng3[] = {1, 0}; +static int ng4[] = {5, 0}; +static unsigned int ng5[] = {3U, 0U}; +static int ng6[] = {31, 0}; +static int ng7[] = {28, 0}; +static int ng8[] = {27, 0}; +static int ng9[] = {24, 0}; +static int ng10[] = {23, 0}; +static int ng11[] = {20, 0}; +static int ng12[] = {19, 0}; +static int ng13[] = {16, 0}; + + + +static void Always_33_0(char *t0) +{ + char t6[8]; + char t22[8]; + char t29[8]; + char t38[8]; + char t40[8]; + char t41[8]; + char t42[8]; + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t7; + char *t8; + char *t9; + char *t10; + char *t11; + char *t12; + char *t13; + char *t14; + char *t15; + char *t16; + unsigned int t17; + unsigned int t18; + unsigned int t19; + unsigned int t20; + unsigned int t21; + unsigned int t23; + unsigned int t24; + unsigned int t25; + unsigned int t26; + unsigned int t27; + unsigned int t28; + char *t30; + unsigned int t31; + unsigned int t32; + unsigned int t33; + unsigned int t34; + unsigned int t35; + unsigned int t36; + char *t37; + char *t39; + char *t43; + char *t44; + char *t45; + char *t46; + char *t47; + char *t48; + unsigned int t49; + int t50; + char *t51; + unsigned int t52; + int t53; + int t54; + char *t55; + unsigned int t56; + int t57; + int t58; + unsigned int t59; + int t60; + unsigned int t61; + unsigned int t62; + int t63; + int t64; + +LAB0: t1 = (t0 + 3160U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(33, ng0); + t2 = (t0 + 3480); + *((int *)t2) = 1; + t3 = (t0 + 3192); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(33, ng0); + +LAB5: xsi_set_current_line(34, ng0); + t4 = ((char*)((ng1))); + t5 = (t0 + 1768); + xsi_vlogvar_assign_value(t5, t4, 0, 0, 4); + xsi_set_current_line(34, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1608); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 4); + xsi_set_current_line(34, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1448); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 4); + xsi_set_current_line(35, ng0); + t2 = (t0 + 1048U); + t3 = *((char **)t2); + t2 = (t0 + 1448); + t4 = (t2 + 56U); + t5 = *((char **)t4); + t7 = (t0 + 1608); + t8 = (t7 + 56U); + t9 = *((char **)t8); + t10 = (t0 + 1768); + t11 = (t10 + 56U); + t12 = *((char **)t11); + t13 = (t0 + 1928); + t14 = (t13 + 56U); + t15 = *((char **)t14); + xsi_vlogtype_concat(t6, 32, 32, 5U, t15, 4, t12, 4, t9, 4, t5, 4, t3, 16); + t16 = (t0 + 2088); + xsi_vlogvar_assign_value(t16, t6, 0, 0, 32); + xsi_set_current_line(37, ng0); + xsi_set_current_line(37, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 2248); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 4); + +LAB6: t2 = (t0 + 2248); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = ((char*)((ng2))); + memset(t6, 0, 8); + t7 = (t4 + 4); + if (*((unsigned int *)t7) != 0) + goto LAB8; + +LAB7: t8 = (t5 + 4); + if (*((unsigned int *)t8) != 0) + goto LAB8; + +LAB11: if (*((unsigned int *)t4) < *((unsigned int *)t5)) + goto LAB9; + +LAB10: t10 = (t6 + 4); + t17 = *((unsigned int *)t10); + t18 = (~(t17)); + t19 = *((unsigned int *)t6); + t20 = (t19 & t18); + t21 = (t20 != 0); + if (t21 > 0) + goto LAB12; + +LAB13: xsi_set_current_line(49, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = ((char*)((ng3))); + memset(t6, 0, 8); + xsi_vlog_unsigned_lshift(t6, 32, t4, 32, t5, 32); + t7 = (t0 + 2088); + xsi_vlogvar_assign_value(t7, t6, 0, 0, 32); + xsi_set_current_line(51, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t6 + 4); + t7 = (t4 + 4); + t17 = *((unsigned int *)t4); + t18 = (t17 >> 28); + *((unsigned int *)t6) = t18; + t19 = *((unsigned int *)t7); + t20 = (t19 >> 28); + *((unsigned int *)t5) = t20; + t21 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t21 & 15U); + t23 = *((unsigned int *)t5); + *((unsigned int *)t5) = (t23 & 15U); + t8 = (t0 + 1928); + xsi_vlogvar_assign_value(t8, t6, 0, 0, 4); + xsi_set_current_line(52, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t6 + 4); + t7 = (t4 + 4); + t17 = *((unsigned int *)t4); + t18 = (t17 >> 24); + *((unsigned int *)t6) = t18; + t19 = *((unsigned int *)t7); + t20 = (t19 >> 24); + *((unsigned int *)t5) = t20; + t21 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t21 & 15U); + t23 = *((unsigned int *)t5); + *((unsigned int *)t5) = (t23 & 15U); + t8 = (t0 + 1768); + xsi_vlogvar_assign_value(t8, t6, 0, 0, 4); + xsi_set_current_line(53, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t6 + 4); + t7 = (t4 + 4); + t17 = *((unsigned int *)t4); + t18 = (t17 >> 20); + *((unsigned int *)t6) = t18; + t19 = *((unsigned int *)t7); + t20 = (t19 >> 20); + *((unsigned int *)t5) = t20; + t21 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t21 & 15U); + t23 = *((unsigned int *)t5); + *((unsigned int *)t5) = (t23 & 15U); + t8 = (t0 + 1608); + xsi_vlogvar_assign_value(t8, t6, 0, 0, 4); + xsi_set_current_line(54, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t6 + 4); + t7 = (t4 + 4); + t17 = *((unsigned int *)t4); + t18 = (t17 >> 16); + *((unsigned int *)t6) = t18; + t19 = *((unsigned int *)t7); + t20 = (t19 >> 16); + *((unsigned int *)t5) = t20; + t21 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t21 & 15U); + t23 = *((unsigned int *)t5); + *((unsigned int *)t5) = (t23 & 15U); + t8 = (t0 + 1448); + xsi_vlogvar_assign_value(t8, t6, 0, 0, 4); + goto LAB2; + +LAB8: t9 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t9) = 1; + goto LAB10; + +LAB9: *((unsigned int *)t6) = 1; + goto LAB10; + +LAB12: xsi_set_current_line(37, ng0); + +LAB14: xsi_set_current_line(38, ng0); + t11 = (t0 + 2088); + t12 = (t11 + 56U); + t13 = *((char **)t12); + t14 = ((char*)((ng3))); + memset(t22, 0, 8); + xsi_vlog_unsigned_lshift(t22, 32, t13, 32, t14, 32); + t15 = (t0 + 2088); + xsi_vlogvar_assign_value(t15, t22, 0, 0, 32); + xsi_set_current_line(39, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t6 + 4); + t7 = (t4 + 4); + t17 = *((unsigned int *)t4); + t18 = (t17 >> 28); + *((unsigned int *)t6) = t18; + t19 = *((unsigned int *)t7); + t20 = (t19 >> 28); + *((unsigned int *)t5) = t20; + t21 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t21 & 15U); + t23 = *((unsigned int *)t5); + *((unsigned int *)t5) = (t23 & 15U); + t8 = ((char*)((ng4))); + memset(t22, 0, 8); + t9 = (t6 + 4); + if (*((unsigned int *)t9) != 0) + goto LAB16; + +LAB15: t10 = (t8 + 4); + if (*((unsigned int *)t10) != 0) + goto LAB16; + +LAB19: if (*((unsigned int *)t6) < *((unsigned int *)t8)) + goto LAB18; + +LAB17: *((unsigned int *)t22) = 1; + +LAB18: t12 = (t22 + 4); + t24 = *((unsigned int *)t12); + t25 = (~(t24)); + t26 = *((unsigned int *)t22); + t27 = (t26 & t25); + t28 = (t27 != 0); + if (t28 > 0) + goto LAB20; + +LAB21: +LAB22: xsi_set_current_line(41, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t6 + 4); + t7 = (t4 + 4); + t17 = *((unsigned int *)t4); + t18 = (t17 >> 24); + *((unsigned int *)t6) = t18; + t19 = *((unsigned int *)t7); + t20 = (t19 >> 24); + *((unsigned int *)t5) = t20; + t21 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t21 & 15U); + t23 = *((unsigned int *)t5); + *((unsigned int *)t5) = (t23 & 15U); + t8 = ((char*)((ng4))); + memset(t22, 0, 8); + t9 = (t6 + 4); + if (*((unsigned int *)t9) != 0) + goto LAB26; + +LAB25: t10 = (t8 + 4); + if (*((unsigned int *)t10) != 0) + goto LAB26; + +LAB29: if (*((unsigned int *)t6) < *((unsigned int *)t8)) + goto LAB28; + +LAB27: *((unsigned int *)t22) = 1; + +LAB28: t12 = (t22 + 4); + t24 = *((unsigned int *)t12); + t25 = (~(t24)); + t26 = *((unsigned int *)t22); + t27 = (t26 & t25); + t28 = (t27 != 0); + if (t28 > 0) + goto LAB30; + +LAB31: +LAB32: xsi_set_current_line(43, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t6 + 4); + t7 = (t4 + 4); + t17 = *((unsigned int *)t4); + t18 = (t17 >> 20); + *((unsigned int *)t6) = t18; + t19 = *((unsigned int *)t7); + t20 = (t19 >> 20); + *((unsigned int *)t5) = t20; + t21 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t21 & 15U); + t23 = *((unsigned int *)t5); + *((unsigned int *)t5) = (t23 & 15U); + t8 = ((char*)((ng4))); + memset(t22, 0, 8); + t9 = (t6 + 4); + if (*((unsigned int *)t9) != 0) + goto LAB36; + +LAB35: t10 = (t8 + 4); + if (*((unsigned int *)t10) != 0) + goto LAB36; + +LAB39: if (*((unsigned int *)t6) < *((unsigned int *)t8)) + goto LAB38; + +LAB37: *((unsigned int *)t22) = 1; + +LAB38: t12 = (t22 + 4); + t24 = *((unsigned int *)t12); + t25 = (~(t24)); + t26 = *((unsigned int *)t22); + t27 = (t26 & t25); + t28 = (t27 != 0); + if (t28 > 0) + goto LAB40; + +LAB41: +LAB42: xsi_set_current_line(45, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t6 + 4); + t7 = (t4 + 4); + t17 = *((unsigned int *)t4); + t18 = (t17 >> 16); + *((unsigned int *)t6) = t18; + t19 = *((unsigned int *)t7); + t20 = (t19 >> 16); + *((unsigned int *)t5) = t20; + t21 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t21 & 15U); + t23 = *((unsigned int *)t5); + *((unsigned int *)t5) = (t23 & 15U); + t8 = ((char*)((ng4))); + memset(t22, 0, 8); + t9 = (t6 + 4); + if (*((unsigned int *)t9) != 0) + goto LAB46; + +LAB45: t10 = (t8 + 4); + if (*((unsigned int *)t10) != 0) + goto LAB46; + +LAB49: if (*((unsigned int *)t6) < *((unsigned int *)t8)) + goto LAB48; + +LAB47: *((unsigned int *)t22) = 1; + +LAB48: t12 = (t22 + 4); + t24 = *((unsigned int *)t12); + t25 = (~(t24)); + t26 = *((unsigned int *)t22); + t27 = (t26 & t25); + t28 = (t27 != 0); + if (t28 > 0) + goto LAB50; + +LAB51: +LAB52: xsi_set_current_line(37, ng0); + t2 = (t0 + 2248); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = ((char*)((ng3))); + memset(t6, 0, 8); + xsi_vlog_unsigned_add(t6, 32, t4, 4, t5, 32); + t7 = (t0 + 2248); + xsi_vlogvar_assign_value(t7, t6, 0, 0, 4); + goto LAB6; + +LAB16: t11 = (t22 + 4); + *((unsigned int *)t22) = 1; + *((unsigned int *)t11) = 1; + goto LAB18; + +LAB20: xsi_set_current_line(40, ng0); + t13 = (t0 + 2088); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memset(t29, 0, 8); + t16 = (t29 + 4); + t30 = (t15 + 4); + t31 = *((unsigned int *)t15); + t32 = (t31 >> 28); + *((unsigned int *)t29) = t32; + t33 = *((unsigned int *)t30); + t34 = (t33 >> 28); + *((unsigned int *)t16) = t34; + t35 = *((unsigned int *)t29); + *((unsigned int *)t29) = (t35 & 15U); + t36 = *((unsigned int *)t16); + *((unsigned int *)t16) = (t36 & 15U); + t37 = ((char*)((ng5))); + memset(t38, 0, 8); + xsi_vlog_unsigned_add(t38, 4, t29, 4, t37, 4); + t39 = (t0 + 2088); + t43 = (t0 + 2088); + t44 = (t43 + 72U); + t45 = *((char **)t44); + t46 = ((char*)((ng6))); + t47 = ((char*)((ng7))); + xsi_vlog_convert_partindices(t40, t41, t42, ((int*)(t45)), 2, t46, 32, 1, t47, 32, 1); + t48 = (t40 + 4); + t49 = *((unsigned int *)t48); + t50 = (!(t49)); + t51 = (t41 + 4); + t52 = *((unsigned int *)t51); + t53 = (!(t52)); + t54 = (t50 && t53); + t55 = (t42 + 4); + t56 = *((unsigned int *)t55); + t57 = (!(t56)); + t58 = (t54 && t57); + if (t58 == 1) + goto LAB23; + +LAB24: goto LAB22; + +LAB23: t59 = *((unsigned int *)t42); + t60 = (t59 + 0); + t61 = *((unsigned int *)t40); + t62 = *((unsigned int *)t41); + t63 = (t61 - t62); + t64 = (t63 + 1); + xsi_vlogvar_assign_value(t39, t38, t60, *((unsigned int *)t41), t64); + goto LAB24; + +LAB26: t11 = (t22 + 4); + *((unsigned int *)t22) = 1; + *((unsigned int *)t11) = 1; + goto LAB28; + +LAB30: xsi_set_current_line(42, ng0); + t13 = (t0 + 2088); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memset(t29, 0, 8); + t16 = (t29 + 4); + t30 = (t15 + 4); + t31 = *((unsigned int *)t15); + t32 = (t31 >> 24); + *((unsigned int *)t29) = t32; + t33 = *((unsigned int *)t30); + t34 = (t33 >> 24); + *((unsigned int *)t16) = t34; + t35 = *((unsigned int *)t29); + *((unsigned int *)t29) = (t35 & 15U); + t36 = *((unsigned int *)t16); + *((unsigned int *)t16) = (t36 & 15U); + t37 = ((char*)((ng5))); + memset(t38, 0, 8); + xsi_vlog_unsigned_add(t38, 4, t29, 4, t37, 4); + t39 = (t0 + 2088); + t43 = (t0 + 2088); + t44 = (t43 + 72U); + t45 = *((char **)t44); + t46 = ((char*)((ng8))); + t47 = ((char*)((ng9))); + xsi_vlog_convert_partindices(t40, t41, t42, ((int*)(t45)), 2, t46, 32, 1, t47, 32, 1); + t48 = (t40 + 4); + t49 = *((unsigned int *)t48); + t50 = (!(t49)); + t51 = (t41 + 4); + t52 = *((unsigned int *)t51); + t53 = (!(t52)); + t54 = (t50 && t53); + t55 = (t42 + 4); + t56 = *((unsigned int *)t55); + t57 = (!(t56)); + t58 = (t54 && t57); + if (t58 == 1) + goto LAB33; + +LAB34: goto LAB32; + +LAB33: t59 = *((unsigned int *)t42); + t60 = (t59 + 0); + t61 = *((unsigned int *)t40); + t62 = *((unsigned int *)t41); + t63 = (t61 - t62); + t64 = (t63 + 1); + xsi_vlogvar_assign_value(t39, t38, t60, *((unsigned int *)t41), t64); + goto LAB34; + +LAB36: t11 = (t22 + 4); + *((unsigned int *)t22) = 1; + *((unsigned int *)t11) = 1; + goto LAB38; + +LAB40: xsi_set_current_line(44, ng0); + t13 = (t0 + 2088); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memset(t29, 0, 8); + t16 = (t29 + 4); + t30 = (t15 + 4); + t31 = *((unsigned int *)t15); + t32 = (t31 >> 20); + *((unsigned int *)t29) = t32; + t33 = *((unsigned int *)t30); + t34 = (t33 >> 20); + *((unsigned int *)t16) = t34; + t35 = *((unsigned int *)t29); + *((unsigned int *)t29) = (t35 & 15U); + t36 = *((unsigned int *)t16); + *((unsigned int *)t16) = (t36 & 15U); + t37 = ((char*)((ng5))); + memset(t38, 0, 8); + xsi_vlog_unsigned_add(t38, 4, t29, 4, t37, 4); + t39 = (t0 + 2088); + t43 = (t0 + 2088); + t44 = (t43 + 72U); + t45 = *((char **)t44); + t46 = ((char*)((ng10))); + t47 = ((char*)((ng11))); + xsi_vlog_convert_partindices(t40, t41, t42, ((int*)(t45)), 2, t46, 32, 1, t47, 32, 1); + t48 = (t40 + 4); + t49 = *((unsigned int *)t48); + t50 = (!(t49)); + t51 = (t41 + 4); + t52 = *((unsigned int *)t51); + t53 = (!(t52)); + t54 = (t50 && t53); + t55 = (t42 + 4); + t56 = *((unsigned int *)t55); + t57 = (!(t56)); + t58 = (t54 && t57); + if (t58 == 1) + goto LAB43; + +LAB44: goto LAB42; + +LAB43: t59 = *((unsigned int *)t42); + t60 = (t59 + 0); + t61 = *((unsigned int *)t40); + t62 = *((unsigned int *)t41); + t63 = (t61 - t62); + t64 = (t63 + 1); + xsi_vlogvar_assign_value(t39, t38, t60, *((unsigned int *)t41), t64); + goto LAB44; + +LAB46: t11 = (t22 + 4); + *((unsigned int *)t22) = 1; + *((unsigned int *)t11) = 1; + goto LAB48; + +LAB50: xsi_set_current_line(46, ng0); + t13 = (t0 + 2088); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memset(t29, 0, 8); + t16 = (t29 + 4); + t30 = (t15 + 4); + t31 = *((unsigned int *)t15); + t32 = (t31 >> 16); + *((unsigned int *)t29) = t32; + t33 = *((unsigned int *)t30); + t34 = (t33 >> 16); + *((unsigned int *)t16) = t34; + t35 = *((unsigned int *)t29); + *((unsigned int *)t29) = (t35 & 15U); + t36 = *((unsigned int *)t16); + *((unsigned int *)t16) = (t36 & 15U); + t37 = ((char*)((ng5))); + memset(t38, 0, 8); + xsi_vlog_unsigned_add(t38, 4, t29, 4, t37, 4); + t39 = (t0 + 2088); + t43 = (t0 + 2088); + t44 = (t43 + 72U); + t45 = *((char **)t44); + t46 = ((char*)((ng12))); + t47 = ((char*)((ng13))); + xsi_vlog_convert_partindices(t40, t41, t42, ((int*)(t45)), 2, t46, 32, 1, t47, 32, 1); + t48 = (t40 + 4); + t49 = *((unsigned int *)t48); + t50 = (!(t49)); + t51 = (t41 + 4); + t52 = *((unsigned int *)t51); + t53 = (!(t52)); + t54 = (t50 && t53); + t55 = (t42 + 4); + t56 = *((unsigned int *)t55); + t57 = (!(t56)); + t58 = (t54 && t57); + if (t58 == 1) + goto LAB53; + +LAB54: goto LAB52; + +LAB53: t59 = *((unsigned int *)t42); + t60 = (t59 + 0); + t61 = *((unsigned int *)t40); + t62 = *((unsigned int *)t41); + t63 = (t61 - t62); + t64 = (t63 + 1); + xsi_vlogvar_assign_value(t39, t38, t60, *((unsigned int *)t41), t64); + goto LAB54; + +} + + +extern void work_m_16012083836245549588_2618506667_init() +{ + static char *pe[] = {(void *)Always_33_0}; + xsi_register_didat("work_m_16012083836245549588_2618506667", "isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16012083836245549588_2618506667.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16012083836245549588_2618506667.didat b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16012083836245549588_2618506667.didat Binary files differnew file mode 100644 index 0000000..59fe66b --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16012083836245549588_2618506667.didat diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16012083836245549588_2618506667.lin64.o b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16012083836245549588_2618506667.lin64.o Binary files differnew file mode 100644 index 0000000..fb68158 --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16012083836245549588_2618506667.lin64.o diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c new file mode 100644 index 0000000..2eba636 --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c @@ -0,0 +1,337 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/verilog/src/glbl.v"; +static unsigned int ng1[] = {1U, 0U}; +static unsigned int ng2[] = {0U, 0U}; + + + +static void NetDecl_16_0(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + unsigned int t8; + unsigned int t9; + char *t10; + unsigned int t11; + unsigned int t12; + char *t13; + unsigned int t14; + unsigned int t15; + char *t16; + +LAB0: t1 = (t0 + 6952U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(16, ng0); + t2 = (t0 + 1960U); + t3 = *((char **)t2); + t2 = (t0 + 8640); + t4 = (t2 + 56U); + t5 = *((char **)t4); + t6 = (t5 + 56U); + t7 = *((char **)t6); + memset(t7, 0, 8); + t8 = 1U; + t9 = t8; + t10 = (t3 + 4); + t11 = *((unsigned int *)t3); + t8 = (t8 & t11); + t12 = *((unsigned int *)t10); + t9 = (t9 & t12); + t13 = (t7 + 4); + t14 = *((unsigned int *)t7); + *((unsigned int *)t7) = (t14 | t8); + t15 = *((unsigned int *)t13); + *((unsigned int *)t13) = (t15 | t9); + xsi_driver_vfirst_trans(t2, 0, 0U); + t16 = (t0 + 8512); + *((int *)t16) = 1; + +LAB1: return; +} + +static void Cont_48_1(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7200U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(48, ng0); + t2 = (t0 + 3640); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8704); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8528); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Cont_49_2(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7448U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(49, ng0); + t2 = (t0 + 3800); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8768); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8544); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Cont_50_3(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7696U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(50, ng0); + t2 = (t0 + 3960); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8832); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8560); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Initial_52_4(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + +LAB0: t1 = (t0 + 7944U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(52, ng0); + +LAB4: xsi_set_current_line(53, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3640); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(54, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3960); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(55, ng0); + t2 = (t0 + 7752); + xsi_process_wait(t2, 100000LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(56, ng0); + t3 = ((char*)((ng2))); + t4 = (t0 + 3640); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + xsi_set_current_line(57, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 3960); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + goto LAB1; + +} + +static void Initial_60_5(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + +LAB0: t1 = (t0 + 8192U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(60, ng0); + +LAB4: xsi_set_current_line(61, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3800); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(62, ng0); + t2 = (t0 + 8000); + xsi_process_wait(t2, 0LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(63, ng0); + t3 = ((char*)((ng2))); + t4 = (t0 + 3800); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + goto LAB1; + +} + + +extern void work_m_16541823861846354283_2073120511_init() +{ + static char *pe[] = {(void *)NetDecl_16_0,(void *)Cont_48_1,(void *)Cont_49_2,(void *)Cont_50_3,(void *)Initial_52_4,(void *)Initial_60_5}; + xsi_register_didat("work_m_16541823861846354283_2073120511", "isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat Binary files differnew file mode 100644 index 0000000..264f658 --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o Binary files differnew file mode 100644 index 0000000..ca1600f --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_17956504886923659924_0893867553.c b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_17956504886923659924_0893867553.c new file mode 100644 index 0000000..8faff9c --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_17956504886923659924_0893867553.c @@ -0,0 +1,108 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab5/TEST_Bin2BCD.v"; +static int ng1[] = {0, 0}; +static int ng2[] = {7, 0}; +static int ng3[] = {16, 0}; +static int ng4[] = {217, 0}; +static int ng5[] = {1839, 0}; + + + +static void Initial_45_0(char *t0) +{ + char *t1; + char *t2; + char *t3; + +LAB0: t1 = (t0 + 2840U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(45, ng0); + +LAB4: xsi_set_current_line(47, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 16); + xsi_set_current_line(50, ng0); + t2 = (t0 + 2648); + xsi_process_wait(t2, 100000LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(51, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 16); + xsi_set_current_line(51, ng0); + t2 = (t0 + 2648); + xsi_process_wait(t2, 50000LL); + *((char **)t1) = &&LAB6; + goto LAB1; + +LAB6: xsi_set_current_line(52, ng0); + t2 = ((char*)((ng3))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 16); + xsi_set_current_line(52, ng0); + t2 = (t0 + 2648); + xsi_process_wait(t2, 50000LL); + *((char **)t1) = &&LAB7; + goto LAB1; + +LAB7: xsi_set_current_line(53, ng0); + t2 = ((char*)((ng4))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 16); + xsi_set_current_line(53, ng0); + t2 = (t0 + 2648); + xsi_process_wait(t2, 50000LL); + *((char **)t1) = &&LAB8; + goto LAB1; + +LAB8: xsi_set_current_line(54, ng0); + t2 = ((char*)((ng5))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 16); + xsi_set_current_line(54, ng0); + t2 = (t0 + 2648); + xsi_process_wait(t2, 50000LL); + *((char **)t1) = &&LAB9; + goto LAB1; + +LAB9: goto LAB1; + +} + + +extern void work_m_17956504886923659924_0893867553_init() +{ + static char *pe[] = {(void *)Initial_45_0}; + xsi_register_didat("work_m_17956504886923659924_0893867553", "isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_17956504886923659924_0893867553.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_17956504886923659924_0893867553.didat b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_17956504886923659924_0893867553.didat Binary files differnew file mode 100644 index 0000000..a107fb0 --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_17956504886923659924_0893867553.didat diff --git a/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_17956504886923659924_0893867553.lin64.o b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_17956504886923659924_0893867553.lin64.o Binary files differnew file mode 100644 index 0000000..3620501 --- /dev/null +++ b/isim/TEST_Bin2BCD_isim_beh.exe.sim/work/m_17956504886923659924_0893867553.lin64.o diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg b/isim/TEST_DisplayController_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg Binary files differnew file mode 100644 index 0000000..f140f5a --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/TEST_DisplayController_isim_beh.exe b/isim/TEST_DisplayController_isim_beh.exe.sim/TEST_DisplayController_isim_beh.exe Binary files differnew file mode 100755 index 0000000..3849b17 --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/TEST_DisplayController_isim_beh.exe diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/isimcrash.log b/isim/TEST_DisplayController_isim_beh.exe.sim/isimcrash.log new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/isimcrash.log diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/isimkernel.log b/isim/TEST_DisplayController_isim_beh.exe.sim/isimkernel.log new file mode 100644 index 0000000..3289a8e --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/isimkernel.log @@ -0,0 +1,29 @@ +Command line: + TEST_DisplayController_isim_beh.exe + -simmode gui + -simrunnum 0 + -socket 47189 + +Thu Mar 29 15:21:49 2012 + + + Elaboration Time: 0.01 sec + + Current Memory Usage: 181.412 Meg + + Total Signals : 33 + Total Nets : 103 + Total Signal Drivers : 19 + Total Blocks : 8 + Total Primitive Blocks : 6 + Total Processes : 27 + Total Traceable Variables : 33 + Total Scalar Nets and Variables : 267 +Total Line Count : 101 + + Total Simulation Time: 0.07 sec + + Current Memory Usage: 256.913 Meg + +Thu Mar 29 15:23:15 2012 + diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/netId.dat b/isim/TEST_DisplayController_isim_beh.exe.sim/netId.dat Binary files differnew file mode 100644 index 0000000..cac5318 --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/netId.dat diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/tmp_save/_1 b/isim/TEST_DisplayController_isim_beh.exe.sim/tmp_save/_1 Binary files differnew file mode 100644 index 0000000..c7f358c --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/tmp_save/_1 diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/TEST_DisplayController_isim_beh.exe_main.c b/isim/TEST_DisplayController_isim_beh.exe.sim/work/TEST_DisplayController_isim_beh.exe_main.c new file mode 100644 index 0000000..1779fbe --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/TEST_DisplayController_isim_beh.exe_main.c @@ -0,0 +1,38 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +#include "xsi.h" + +struct XSI_INFO xsi_info; + + + +int main(int argc, char **argv) +{ + xsi_init_design(argc, argv); + xsi_register_info(&xsi_info); + + xsi_register_min_prec_unit(-12); + work_m_09461933616065074075_2531671071_init(); + work_m_00071202231550837446_1606112044_init(); + work_m_13807125322707046414_3845763652_init(); + work_m_07373066261735772851_1207358656_init(); + work_m_16541823861846354283_2073120511_init(); + + + xsi_register_tops("work_m_07373066261735772851_1207358656"); + xsi_register_tops("work_m_16541823861846354283_2073120511"); + + + return xsi_run_simulation(argc, argv); + +} diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/TEST_DisplayController_isim_beh.exe_main.lin64.o b/isim/TEST_DisplayController_isim_beh.exe.sim/work/TEST_DisplayController_isim_beh.exe_main.lin64.o Binary files differnew file mode 100644 index 0000000..c198deb --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/TEST_DisplayController_isim_beh.exe_main.lin64.o diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_00071202231550837446_1606112044.c b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_00071202231550837446_1606112044.c new file mode 100644 index 0000000..1821891 --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_00071202231550837446_1606112044.c @@ -0,0 +1,205 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab5/SevSegDisp.v"; +static unsigned int ng1[] = {0U, 0U}; +static unsigned int ng2[] = {1U, 0U}; +static unsigned int ng3[] = {79U, 0U}; +static unsigned int ng4[] = {2U, 0U}; +static unsigned int ng5[] = {18U, 0U}; +static unsigned int ng6[] = {3U, 0U}; +static unsigned int ng7[] = {6U, 0U}; +static unsigned int ng8[] = {4U, 0U}; +static unsigned int ng9[] = {76U, 0U}; +static unsigned int ng10[] = {5U, 0U}; +static unsigned int ng11[] = {36U, 0U}; +static unsigned int ng12[] = {32U, 0U}; +static unsigned int ng13[] = {7U, 0U}; +static unsigned int ng14[] = {15U, 0U}; +static unsigned int ng15[] = {8U, 0U}; +static unsigned int ng16[] = {9U, 0U}; +static unsigned int ng17[] = {12U, 0U}; +static unsigned int ng18[] = {26U, 0U}; + + + +static void Always_29_0(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + int t6; + char *t7; + char *t8; + +LAB0: t1 = (t0 + 2360U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(29, ng0); + t2 = (t0 + 2680); + *((int *)t2) = 1; + t3 = (t0 + 2392); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(29, ng0); + +LAB5: xsi_set_current_line(30, ng0); + t4 = (t0 + 1048U); + t5 = *((char **)t4); + +LAB6: t4 = ((char*)((ng1))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t4, 4); + if (t6 == 1) + goto LAB7; + +LAB8: t2 = ((char*)((ng2))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB9; + +LAB10: t2 = ((char*)((ng4))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB11; + +LAB12: t2 = ((char*)((ng6))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB13; + +LAB14: t2 = ((char*)((ng8))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB15; + +LAB16: t2 = ((char*)((ng10))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB17; + +LAB18: t2 = ((char*)((ng7))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB19; + +LAB20: t2 = ((char*)((ng13))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB21; + +LAB22: t2 = ((char*)((ng15))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB23; + +LAB24: t2 = ((char*)((ng16))); + t6 = xsi_vlog_unsigned_case_compare(t5, 4, t2, 4); + if (t6 == 1) + goto LAB25; + +LAB26: +LAB28: +LAB27: xsi_set_current_line(41, ng0); + t2 = ((char*)((ng18))); + t3 = (t0 + 1448); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 7); + +LAB29: goto LAB2; + +LAB7: xsi_set_current_line(31, ng0); + t7 = ((char*)((ng2))); + t8 = (t0 + 1448); + xsi_vlogvar_assign_value(t8, t7, 0, 0, 7); + goto LAB29; + +LAB9: xsi_set_current_line(32, ng0); + t3 = ((char*)((ng3))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +LAB11: xsi_set_current_line(33, ng0); + t3 = ((char*)((ng5))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +LAB13: xsi_set_current_line(34, ng0); + t3 = ((char*)((ng7))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +LAB15: xsi_set_current_line(35, ng0); + t3 = ((char*)((ng9))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +LAB17: xsi_set_current_line(36, ng0); + t3 = ((char*)((ng11))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +LAB19: xsi_set_current_line(37, ng0); + t3 = ((char*)((ng12))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +LAB21: xsi_set_current_line(38, ng0); + t3 = ((char*)((ng14))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +LAB23: xsi_set_current_line(39, ng0); + t3 = ((char*)((ng1))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +LAB25: xsi_set_current_line(40, ng0); + t3 = ((char*)((ng17))); + t4 = (t0 + 1448); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 7); + goto LAB29; + +} + + +extern void work_m_00071202231550837446_1606112044_init() +{ + static char *pe[] = {(void *)Always_29_0}; + xsi_register_didat("work_m_00071202231550837446_1606112044", "isim/TEST_DisplayController_isim_beh.exe.sim/work/m_00071202231550837446_1606112044.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_00071202231550837446_1606112044.didat b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_00071202231550837446_1606112044.didat Binary files differnew file mode 100644 index 0000000..1122044 --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_00071202231550837446_1606112044.didat diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_00071202231550837446_1606112044.lin64.o b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_00071202231550837446_1606112044.lin64.o Binary files differnew file mode 100644 index 0000000..c5071ec --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_00071202231550837446_1606112044.lin64.o diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_07373066261735772851_1207358656.c b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_07373066261735772851_1207358656.c new file mode 100644 index 0000000..c17904b --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_07373066261735772851_1207358656.c @@ -0,0 +1,201 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab5/TEST_DisplayController.v"; +static int ng1[] = {0, 0}; +static unsigned int ng2[] = {3U, 0U}; +static unsigned int ng3[] = {0U, 0U}; +static unsigned int ng4[] = {7U, 0U}; +static unsigned int ng5[] = {9U, 0U}; +static int ng6[] = {1, 0}; + + + +static void Initial_51_0(char *t0) +{ + char t9[8]; + char *t1; + char *t2; + char *t3; + unsigned int t4; + unsigned int t5; + unsigned int t6; + unsigned int t7; + unsigned int t8; + char *t10; + char *t11; + char *t12; + char *t13; + unsigned int t14; + unsigned int t15; + unsigned int t16; + unsigned int t17; + unsigned int t18; + char *t19; + char *t20; + char *t21; + unsigned int t22; + unsigned int t23; + unsigned int t24; + unsigned int t25; + unsigned int t26; + unsigned int t27; + unsigned int t28; + unsigned int t29; + char *t30; + +LAB0: t1 = (t0 + 3320U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(51, ng0); + +LAB4: xsi_set_current_line(53, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1608); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 4); + xsi_set_current_line(54, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1768); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 4); + xsi_set_current_line(55, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 4); + xsi_set_current_line(56, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 2088); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 4); + xsi_set_current_line(57, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 2248); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(58, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 2408); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(61, ng0); + t2 = (t0 + 3128); + xsi_process_wait(t2, 100000LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(62, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 1608); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 4); + xsi_set_current_line(63, ng0); + t2 = ((char*)((ng3))); + t3 = (t0 + 1768); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 4); + xsi_set_current_line(64, ng0); + t2 = ((char*)((ng4))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 4); + xsi_set_current_line(65, ng0); + t2 = ((char*)((ng5))); + t3 = (t0 + 2088); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 4); + xsi_set_current_line(66, ng0); + +LAB6: t2 = ((char*)((ng6))); + t3 = (t2 + 4); + t4 = *((unsigned int *)t3); + t5 = (~(t4)); + t6 = *((unsigned int *)t2); + t7 = (t6 & t5); + t8 = (t7 != 0); + if (t8 > 0) + goto LAB7; + +LAB8: goto LAB1; + +LAB7: xsi_set_current_line(66, ng0); + +LAB9: xsi_set_current_line(67, ng0); + t10 = (t0 + 2248); + t11 = (t10 + 56U); + t12 = *((char **)t11); + memset(t9, 0, 8); + t13 = (t12 + 4); + t14 = *((unsigned int *)t13); + t15 = (~(t14)); + t16 = *((unsigned int *)t12); + t17 = (t16 & t15); + t18 = (t17 & 1U); + if (t18 != 0) + goto LAB13; + +LAB11: if (*((unsigned int *)t13) == 0) + goto LAB10; + +LAB12: t19 = (t9 + 4); + *((unsigned int *)t9) = 1; + *((unsigned int *)t19) = 1; + +LAB13: t20 = (t9 + 4); + t21 = (t12 + 4); + t22 = *((unsigned int *)t12); + t23 = (~(t22)); + *((unsigned int *)t9) = t23; + *((unsigned int *)t20) = 0; + if (*((unsigned int *)t21) != 0) + goto LAB15; + +LAB14: t28 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t28 & 1U); + t29 = *((unsigned int *)t20); + *((unsigned int *)t20) = (t29 & 1U); + t30 = (t0 + 2248); + xsi_vlogvar_assign_value(t30, t9, 0, 0, 1); + xsi_set_current_line(67, ng0); + t2 = (t0 + 3128); + xsi_process_wait(t2, 1000LL); + *((char **)t1) = &&LAB16; + goto LAB1; + +LAB10: *((unsigned int *)t9) = 1; + goto LAB13; + +LAB15: t24 = *((unsigned int *)t9); + t25 = *((unsigned int *)t21); + *((unsigned int *)t9) = (t24 | t25); + t26 = *((unsigned int *)t20); + t27 = *((unsigned int *)t21); + *((unsigned int *)t20) = (t26 | t27); + goto LAB14; + +LAB16: goto LAB6; + +} + + +extern void work_m_07373066261735772851_1207358656_init() +{ + static char *pe[] = {(void *)Initial_51_0}; + xsi_register_didat("work_m_07373066261735772851_1207358656", "isim/TEST_DisplayController_isim_beh.exe.sim/work/m_07373066261735772851_1207358656.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_07373066261735772851_1207358656.didat b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_07373066261735772851_1207358656.didat Binary files differnew file mode 100644 index 0000000..a965f9b --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_07373066261735772851_1207358656.didat diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_07373066261735772851_1207358656.lin64.o b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_07373066261735772851_1207358656.lin64.o Binary files differnew file mode 100644 index 0000000..62b04bc --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_07373066261735772851_1207358656.lin64.o diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.c b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.c new file mode 100644 index 0000000..7788485 --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.c @@ -0,0 +1,274 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab5/ClockDivider.v"; +static int ng1[] = {1, 0}; +static int ng2[] = {0, 0}; +static unsigned int ng3[] = {1U, 0U}; + + + +static void Always_31_0(char *t0) +{ + char t6[8]; + char t30[8]; + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t7; + char *t8; + unsigned int t9; + unsigned int t10; + unsigned int t11; + unsigned int t12; + unsigned int t13; + unsigned int t14; + unsigned int t15; + unsigned int t16; + unsigned int t17; + unsigned int t18; + unsigned int t19; + unsigned int t20; + char *t21; + char *t22; + unsigned int t23; + unsigned int t24; + unsigned int t25; + unsigned int t26; + unsigned int t27; + char *t28; + char *t29; + char *t31; + char *t32; + unsigned int t33; + unsigned int t34; + unsigned int t35; + unsigned int t36; + unsigned int t37; + char *t38; + char *t39; + char *t40; + unsigned int t41; + unsigned int t42; + unsigned int t43; + unsigned int t44; + unsigned int t45; + unsigned int t46; + unsigned int t47; + unsigned int t48; + char *t49; + +LAB0: t1 = (t0 + 2840U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(31, ng0); + t2 = (t0 + 3160); + *((int *)t2) = 1; + t3 = (t0 + 2872); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(31, ng0); + +LAB5: xsi_set_current_line(32, ng0); + t4 = (t0 + 1208U); + t5 = *((char **)t4); + t4 = ((char*)((ng1))); + memset(t6, 0, 8); + t7 = (t5 + 4); + t8 = (t4 + 4); + t9 = *((unsigned int *)t5); + t10 = *((unsigned int *)t4); + t11 = (t9 ^ t10); + t12 = *((unsigned int *)t7); + t13 = *((unsigned int *)t8); + t14 = (t12 ^ t13); + t15 = (t11 | t14); + t16 = *((unsigned int *)t7); + t17 = *((unsigned int *)t8); + t18 = (t16 | t17); + t19 = (~(t18)); + t20 = (t15 & t19); + if (t20 != 0) + goto LAB9; + +LAB6: if (t18 != 0) + goto LAB8; + +LAB7: *((unsigned int *)t6) = 1; + +LAB9: t22 = (t6 + 4); + t23 = *((unsigned int *)t22); + t24 = (~(t23)); + t25 = *((unsigned int *)t6); + t26 = (t25 & t24); + t27 = (t26 != 0); + if (t27 > 0) + goto LAB10; + +LAB11: xsi_set_current_line(35, ng0); + t2 = (t0 + 1928); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 1368U); + t7 = *((char **)t5); + memset(t6, 0, 8); + t5 = (t4 + 4); + t8 = (t7 + 4); + t9 = *((unsigned int *)t4); + t10 = *((unsigned int *)t7); + t11 = (t9 ^ t10); + t12 = *((unsigned int *)t5); + t13 = *((unsigned int *)t8); + t14 = (t12 ^ t13); + t15 = (t11 | t14); + t16 = *((unsigned int *)t5); + t17 = *((unsigned int *)t8); + t18 = (t16 | t17); + t19 = (~(t18)); + t20 = (t15 & t19); + if (t20 != 0) + goto LAB17; + +LAB14: if (t18 != 0) + goto LAB16; + +LAB15: *((unsigned int *)t6) = 1; + +LAB17: t22 = (t6 + 4); + t23 = *((unsigned int *)t22); + t24 = (~(t23)); + t25 = *((unsigned int *)t6); + t26 = (t25 & t24); + t27 = (t26 != 0); + if (t27 > 0) + goto LAB18; + +LAB19: xsi_set_current_line(38, ng0); + +LAB28: xsi_set_current_line(39, ng0); + t2 = (t0 + 1928); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = ((char*)((ng3))); + memset(t6, 0, 8); + xsi_vlog_unsigned_add(t6, 24, t4, 24, t5, 24); + t7 = (t0 + 1928); + xsi_vlogvar_assign_value(t7, t6, 0, 0, 24); + +LAB20: +LAB12: goto LAB2; + +LAB8: t21 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t21) = 1; + goto LAB9; + +LAB10: xsi_set_current_line(32, ng0); + +LAB13: xsi_set_current_line(33, ng0); + t28 = ((char*)((ng2))); + t29 = (t0 + 1928); + xsi_vlogvar_assign_value(t29, t28, 0, 0, 24); + xsi_set_current_line(34, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 1768); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + goto LAB12; + +LAB16: t21 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t21) = 1; + goto LAB17; + +LAB18: xsi_set_current_line(35, ng0); + +LAB21: xsi_set_current_line(36, ng0); + t28 = (t0 + 1768); + t29 = (t28 + 56U); + t31 = *((char **)t29); + memset(t30, 0, 8); + t32 = (t31 + 4); + t33 = *((unsigned int *)t32); + t34 = (~(t33)); + t35 = *((unsigned int *)t31); + t36 = (t35 & t34); + t37 = (t36 & 1U); + if (t37 != 0) + goto LAB25; + +LAB23: if (*((unsigned int *)t32) == 0) + goto LAB22; + +LAB24: t38 = (t30 + 4); + *((unsigned int *)t30) = 1; + *((unsigned int *)t38) = 1; + +LAB25: t39 = (t30 + 4); + t40 = (t31 + 4); + t41 = *((unsigned int *)t31); + t42 = (~(t41)); + *((unsigned int *)t30) = t42; + *((unsigned int *)t39) = 0; + if (*((unsigned int *)t40) != 0) + goto LAB27; + +LAB26: t47 = *((unsigned int *)t30); + *((unsigned int *)t30) = (t47 & 1U); + t48 = *((unsigned int *)t39); + *((unsigned int *)t39) = (t48 & 1U); + t49 = (t0 + 1768); + xsi_vlogvar_assign_value(t49, t30, 0, 0, 1); + xsi_set_current_line(37, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 24); + goto LAB20; + +LAB22: *((unsigned int *)t30) = 1; + goto LAB25; + +LAB27: t43 = *((unsigned int *)t30); + t44 = *((unsigned int *)t40); + *((unsigned int *)t30) = (t43 | t44); + t45 = *((unsigned int *)t39); + t46 = *((unsigned int *)t40); + *((unsigned int *)t39) = (t45 | t46); + goto LAB26; + +} + + +extern void work_m_09461933616065074075_2531671071_init() +{ + static char *pe[] = {(void *)Always_31_0}; + xsi_register_didat("work_m_09461933616065074075_2531671071", "isim/TEST_DisplayController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.didat b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.didat Binary files differnew file mode 100644 index 0000000..7c263e9 --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.didat diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.lin64.o b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.lin64.o Binary files differnew file mode 100644 index 0000000..4ef30dd --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.lin64.o diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_13807125322707046414_3845763652.c b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_13807125322707046414_3845763652.c new file mode 100644 index 0000000..80c2cea --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_13807125322707046414_3845763652.c @@ -0,0 +1,219 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab5/DisplayController.v"; +static unsigned int ng1[] = {1U, 0U}; +static unsigned int ng2[] = {0U, 0U}; +static unsigned int ng3[] = {14U, 0U}; +static unsigned int ng4[] = {13U, 0U}; +static unsigned int ng5[] = {2U, 0U}; +static unsigned int ng6[] = {11U, 0U}; +static unsigned int ng7[] = {3U, 0U}; +static unsigned int ng8[] = {7U, 0U}; +static int ng9[] = {10, 0}; + + + +static void Always_48_0(char *t0) +{ + char t8[8]; + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t9; + int t10; + +LAB0: t1 = (t0 + 4440U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(48, ng0); + t2 = (t0 + 5008); + *((int *)t2) = 1; + t3 = (t0 + 4472); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(48, ng0); + +LAB5: xsi_set_current_line(49, ng0); + t4 = (t0 + 3528); + t5 = (t4 + 56U); + t6 = *((char **)t5); + t7 = ((char*)((ng1))); + memset(t8, 0, 8); + xsi_vlog_unsigned_add(t8, 2, t6, 2, t7, 2); + t9 = (t0 + 3528); + xsi_vlogvar_wait_assign_value(t9, t8, 0, 0, 2, 0LL); + xsi_set_current_line(50, ng0); + t2 = (t0 + 3528); + t3 = (t2 + 56U); + t4 = *((char **)t3); + +LAB6: t5 = ((char*)((ng2))); + t10 = xsi_vlog_unsigned_case_compare(t4, 2, t5, 2); + if (t10 == 1) + goto LAB7; + +LAB8: t2 = ((char*)((ng1))); + t10 = xsi_vlog_unsigned_case_compare(t4, 2, t2, 2); + if (t10 == 1) + goto LAB9; + +LAB10: t2 = ((char*)((ng5))); + t10 = xsi_vlog_unsigned_case_compare(t4, 2, t2, 2); + if (t10 == 1) + goto LAB11; + +LAB12: t2 = ((char*)((ng7))); + t10 = xsi_vlog_unsigned_case_compare(t4, 2, t2, 2); + if (t10 == 1) + goto LAB13; + +LAB14: +LAB15: xsi_set_current_line(56, ng0); + t2 = (t0 + 3528); + t3 = (t2 + 56U); + t5 = *((char **)t3); + +LAB16: t6 = ((char*)((ng2))); + t10 = xsi_vlog_unsigned_case_compare(t5, 2, t6, 2); + if (t10 == 1) + goto LAB17; + +LAB18: t2 = ((char*)((ng1))); + t10 = xsi_vlog_unsigned_case_compare(t5, 2, t2, 2); + if (t10 == 1) + goto LAB19; + +LAB20: t2 = ((char*)((ng5))); + t10 = xsi_vlog_unsigned_case_compare(t5, 2, t2, 2); + if (t10 == 1) + goto LAB21; + +LAB22: t2 = ((char*)((ng7))); + t10 = xsi_vlog_unsigned_case_compare(t5, 2, t2, 2); + if (t10 == 1) + goto LAB23; + +LAB24: +LAB25: goto LAB2; + +LAB7: xsi_set_current_line(51, ng0); + t6 = ((char*)((ng3))); + t7 = (t0 + 3368); + xsi_vlogvar_wait_assign_value(t7, t6, 0, 0, 4, 0LL); + goto LAB15; + +LAB9: xsi_set_current_line(52, ng0); + t3 = ((char*)((ng4))); + t5 = (t0 + 3368); + xsi_vlogvar_wait_assign_value(t5, t3, 0, 0, 4, 0LL); + goto LAB15; + +LAB11: xsi_set_current_line(53, ng0); + t3 = ((char*)((ng6))); + t5 = (t0 + 3368); + xsi_vlogvar_wait_assign_value(t5, t3, 0, 0, 4, 0LL); + goto LAB15; + +LAB13: xsi_set_current_line(54, ng0); + t3 = ((char*)((ng8))); + t5 = (t0 + 3368); + xsi_vlogvar_wait_assign_value(t5, t3, 0, 0, 4, 0LL); + goto LAB15; + +LAB17: xsi_set_current_line(57, ng0); + t7 = (t0 + 2168U); + t9 = *((char **)t7); + t7 = (t0 + 3208); + xsi_vlogvar_wait_assign_value(t7, t9, 0, 0, 7, 0LL); + goto LAB25; + +LAB19: xsi_set_current_line(58, ng0); + t3 = (t0 + 2328U); + t6 = *((char **)t3); + t3 = (t0 + 3208); + xsi_vlogvar_wait_assign_value(t3, t6, 0, 0, 7, 0LL); + goto LAB25; + +LAB21: xsi_set_current_line(59, ng0); + t3 = (t0 + 2488U); + t6 = *((char **)t3); + t3 = (t0 + 3208); + xsi_vlogvar_wait_assign_value(t3, t6, 0, 0, 7, 0LL); + goto LAB25; + +LAB23: xsi_set_current_line(60, ng0); + t3 = (t0 + 2648U); + t6 = *((char **)t3); + t3 = (t0 + 3208); + xsi_vlogvar_wait_assign_value(t3, t6, 0, 0, 7, 0LL); + goto LAB25; + +} + +static void implSig1_execute(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + +LAB0: t1 = (t0 + 4688U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: t2 = ((char*)((ng9))); + t3 = (t0 + 5088); + t4 = (t3 + 56U); + t5 = *((char **)t4); + t6 = (t5 + 56U); + t7 = *((char **)t6); + memcpy(t7, t2, 8); + xsi_driver_vfirst_trans(t3, 0, 31); + +LAB1: return; +} + + +extern void work_m_13807125322707046414_3845763652_init() +{ + static char *pe[] = {(void *)Always_48_0,(void *)implSig1_execute}; + xsi_register_didat("work_m_13807125322707046414_3845763652", "isim/TEST_DisplayController_isim_beh.exe.sim/work/m_13807125322707046414_3845763652.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_13807125322707046414_3845763652.didat b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_13807125322707046414_3845763652.didat Binary files differnew file mode 100644 index 0000000..fe61d19 --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_13807125322707046414_3845763652.didat diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_13807125322707046414_3845763652.lin64.o b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_13807125322707046414_3845763652.lin64.o Binary files differnew file mode 100644 index 0000000..a164a66 --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_13807125322707046414_3845763652.lin64.o diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c new file mode 100644 index 0000000..4fa48eb --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c @@ -0,0 +1,337 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/verilog/src/glbl.v"; +static unsigned int ng1[] = {1U, 0U}; +static unsigned int ng2[] = {0U, 0U}; + + + +static void NetDecl_16_0(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + unsigned int t8; + unsigned int t9; + char *t10; + unsigned int t11; + unsigned int t12; + char *t13; + unsigned int t14; + unsigned int t15; + char *t16; + +LAB0: t1 = (t0 + 6952U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(16, ng0); + t2 = (t0 + 1960U); + t3 = *((char **)t2); + t2 = (t0 + 8640); + t4 = (t2 + 56U); + t5 = *((char **)t4); + t6 = (t5 + 56U); + t7 = *((char **)t6); + memset(t7, 0, 8); + t8 = 1U; + t9 = t8; + t10 = (t3 + 4); + t11 = *((unsigned int *)t3); + t8 = (t8 & t11); + t12 = *((unsigned int *)t10); + t9 = (t9 & t12); + t13 = (t7 + 4); + t14 = *((unsigned int *)t7); + *((unsigned int *)t7) = (t14 | t8); + t15 = *((unsigned int *)t13); + *((unsigned int *)t13) = (t15 | t9); + xsi_driver_vfirst_trans(t2, 0, 0U); + t16 = (t0 + 8512); + *((int *)t16) = 1; + +LAB1: return; +} + +static void Cont_48_1(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7200U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(48, ng0); + t2 = (t0 + 3640); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8704); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8528); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Cont_49_2(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7448U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(49, ng0); + t2 = (t0 + 3800); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8768); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8544); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Cont_50_3(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7696U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(50, ng0); + t2 = (t0 + 3960); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8832); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8560); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Initial_52_4(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + +LAB0: t1 = (t0 + 7944U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(52, ng0); + +LAB4: xsi_set_current_line(53, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3640); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(54, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3960); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(55, ng0); + t2 = (t0 + 7752); + xsi_process_wait(t2, 100000LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(56, ng0); + t3 = ((char*)((ng2))); + t4 = (t0 + 3640); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + xsi_set_current_line(57, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 3960); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + goto LAB1; + +} + +static void Initial_60_5(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + +LAB0: t1 = (t0 + 8192U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(60, ng0); + +LAB4: xsi_set_current_line(61, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3800); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(62, ng0); + t2 = (t0 + 8000); + xsi_process_wait(t2, 0LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(63, ng0); + t3 = ((char*)((ng2))); + t4 = (t0 + 3800); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + goto LAB1; + +} + + +extern void work_m_16541823861846354283_2073120511_init() +{ + static char *pe[] = {(void *)NetDecl_16_0,(void *)Cont_48_1,(void *)Cont_49_2,(void *)Cont_50_3,(void *)Initial_52_4,(void *)Initial_60_5}; + xsi_register_didat("work_m_16541823861846354283_2073120511", "isim/TEST_DisplayController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat Binary files differnew file mode 100644 index 0000000..f31cbd9 --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat diff --git a/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o Binary files differnew file mode 100644 index 0000000..c0663ec --- /dev/null +++ b/isim/TEST_DisplayController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg b/isim/TEST_FirFilter_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg Binary files differnew file mode 100644 index 0000000..3ad9796 --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/TEST_FirFilter_isim_beh.exe b/isim/TEST_FirFilter_isim_beh.exe.sim/TEST_FirFilter_isim_beh.exe Binary files differnew file mode 100755 index 0000000..9ae8614 --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/TEST_FirFilter_isim_beh.exe diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/isimcrash.log b/isim/TEST_FirFilter_isim_beh.exe.sim/isimcrash.log new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/isimcrash.log diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/isimkernel.log b/isim/TEST_FirFilter_isim_beh.exe.sim/isimkernel.log new file mode 100644 index 0000000..7261d05 --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/isimkernel.log @@ -0,0 +1,29 @@ +Command line: + TEST_FirFilter_isim_beh.exe + -simmode gui + -simrunnum 0 + -socket 57336 + +Thu Mar 29 16:01:28 2012 + + + Elaboration Time: 0.02 sec + + Current Memory Usage: 181.268 Meg + + Total Signals : 17 + Total Nets : 39 + Total Signal Drivers : 9 + Total Blocks : 3 + Total Primitive Blocks : 2 + Total Processes : 13 + Total Traceable Variables : 24 + Total Scalar Nets and Variables : 177 +Total Line Count : 30 + + Total Simulation Time: 0.06 sec + + Current Memory Usage: 256.77 Meg + +Thu Mar 29 16:03:49 2012 + diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/netId.dat b/isim/TEST_FirFilter_isim_beh.exe.sim/netId.dat Binary files differnew file mode 100644 index 0000000..825c226 --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/netId.dat diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/tmp_save/_1 b/isim/TEST_FirFilter_isim_beh.exe.sim/tmp_save/_1 Binary files differnew file mode 100644 index 0000000..e20c7cc --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/tmp_save/_1 diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/work/TEST_FirFilter_isim_beh.exe_main.c b/isim/TEST_FirFilter_isim_beh.exe.sim/work/TEST_FirFilter_isim_beh.exe_main.c new file mode 100644 index 0000000..aa6756f --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/work/TEST_FirFilter_isim_beh.exe_main.c @@ -0,0 +1,36 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +#include "xsi.h" + +struct XSI_INFO xsi_info; + + + +int main(int argc, char **argv) +{ + xsi_init_design(argc, argv); + xsi_register_info(&xsi_info); + + xsi_register_min_prec_unit(-12); + work_m_05679693179034758439_1243158022_init(); + work_m_11346574241544900769_1316107190_init(); + work_m_16541823861846354283_2073120511_init(); + + + xsi_register_tops("work_m_11346574241544900769_1316107190"); + xsi_register_tops("work_m_16541823861846354283_2073120511"); + + + return xsi_run_simulation(argc, argv); + +} diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/work/TEST_FirFilter_isim_beh.exe_main.lin64.o b/isim/TEST_FirFilter_isim_beh.exe.sim/work/TEST_FirFilter_isim_beh.exe_main.lin64.o Binary files differnew file mode 100644 index 0000000..7a89d4c --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/work/TEST_FirFilter_isim_beh.exe_main.lin64.o diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_05679693179034758439_1243158022.c b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_05679693179034758439_1243158022.c new file mode 100644 index 0000000..2e7841e --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_05679693179034758439_1243158022.c @@ -0,0 +1,171 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab5/FIRFilter.v"; +static int ng1[] = {0, 0}; +static int ng2[] = {20, 0}; +static int ng3[] = {15, 0}; +static int ng4[] = {10, 0}; + + + +static void Always_33_0(char *t0) +{ + char t13[8]; + char t14[8]; + char t15[8]; + char t20[8]; + char t21[8]; + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + unsigned int t6; + unsigned int t7; + unsigned int t8; + unsigned int t9; + unsigned int t10; + char *t11; + char *t12; + char *t16; + char *t17; + char *t18; + char *t19; + char *t22; + +LAB0: t1 = (t0 + 3000U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(33, ng0); + t2 = (t0 + 3568); + *((int *)t2) = 1; + t3 = (t0 + 3032); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(33, ng0); + +LAB5: xsi_set_current_line(34, ng0); + t4 = (t0 + 1368U); + t5 = *((char **)t4); + t4 = (t5 + 4); + t6 = *((unsigned int *)t4); + t7 = (~(t6)); + t8 = *((unsigned int *)t5); + t9 = (t8 & t7); + t10 = (t9 != 0); + if (t10 > 0) + goto LAB6; + +LAB7: xsi_set_current_line(37, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 1048U); + t4 = *((char **)t3); + memset(t13, 0, 8); + xsi_vlog_unsigned_multiply(t13, 32, t2, 32, t4, 8); + t3 = ((char*)((ng3))); + t5 = (t0 + 1928); + t11 = (t5 + 56U); + t12 = *((char **)t11); + memset(t14, 0, 8); + xsi_vlog_unsigned_multiply(t14, 32, t3, 32, t12, 16); + memset(t15, 0, 8); + xsi_vlog_unsigned_add(t15, 32, t13, 32, t14, 32); + t16 = ((char*)((ng4))); + t17 = (t0 + 2088); + t18 = (t17 + 56U); + t19 = *((char **)t18); + memset(t20, 0, 8); + xsi_vlog_unsigned_multiply(t20, 32, t16, 32, t19, 16); + memset(t21, 0, 8); + xsi_vlog_unsigned_add(t21, 32, t15, 32, t20, 32); + t22 = (t0 + 1768); + xsi_vlogvar_assign_value(t22, t21, 0, 0, 16); + +LAB8: goto LAB2; + +LAB6: xsi_set_current_line(35, ng0); + t11 = ((char*)((ng1))); + t12 = (t0 + 1768); + xsi_vlogvar_assign_value(t12, t11, 0, 0, 16); + goto LAB8; + +} + +static void Always_40_1(char *t0) +{ + char t8[8]; + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + +LAB0: t1 = (t0 + 3248U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(40, ng0); + t2 = (t0 + 3584); + *((int *)t2) = 1; + t3 = (t0 + 3280); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(40, ng0); + +LAB5: xsi_set_current_line(41, ng0); + t4 = (t0 + 1928); + t5 = (t4 + 56U); + t6 = *((char **)t5); + t7 = (t0 + 2088); + xsi_vlogvar_assign_value(t7, t6, 0, 0, 16); + xsi_set_current_line(42, ng0); + t2 = (t0 + 1048U); + t3 = *((char **)t2); + memcpy(t8, t3, 8); + t2 = (t0 + 1928); + xsi_vlogvar_assign_value(t2, t8, 0, 0, 16); + goto LAB2; + +} + + +extern void work_m_05679693179034758439_1243158022_init() +{ + static char *pe[] = {(void *)Always_33_0,(void *)Always_40_1}; + xsi_register_didat("work_m_05679693179034758439_1243158022", "isim/TEST_FirFilter_isim_beh.exe.sim/work/m_05679693179034758439_1243158022.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_05679693179034758439_1243158022.didat b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_05679693179034758439_1243158022.didat Binary files differnew file mode 100644 index 0000000..2271f55 --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_05679693179034758439_1243158022.didat diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_05679693179034758439_1243158022.lin64.o b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_05679693179034758439_1243158022.lin64.o Binary files differnew file mode 100644 index 0000000..9ab54e7 --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_05679693179034758439_1243158022.lin64.o diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_11346574241544900769_1316107190.c b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_11346574241544900769_1316107190.c new file mode 100644 index 0000000..c811826 --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_11346574241544900769_1316107190.c @@ -0,0 +1,198 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab5/TEST_FirFilter.v"; +static int ng1[] = {0, 0}; +static int ng2[] = {100, 0}; +static int ng3[] = {1, 0}; +static int ng4[] = {12, 0}; +static int ng5[] = {157, 0}; +static int ng6[] = {56, 0}; + + + +static void Initial_43_0(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + +LAB0: t1 = (t0 + 2680U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(43, ng0); + +LAB4: xsi_set_current_line(45, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1448); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 8); + xsi_set_current_line(46, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1608); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(47, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1768); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(50, ng0); + t2 = (t0 + 2488); + xsi_process_wait(t2, 100000LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(53, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 1448); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 8); + xsi_set_current_line(53, ng0); + t2 = (t0 + 2488); + xsi_process_wait(t2, 10000LL); + *((char **)t1) = &&LAB6; + goto LAB1; + +LAB6: xsi_set_current_line(53, ng0); + t2 = ((char*)((ng3))); + t3 = (t0 + 1608); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(53, ng0); + t2 = (t0 + 2488); + xsi_process_wait(t2, 10000LL); + *((char **)t1) = &&LAB7; + goto LAB1; + +LAB7: xsi_set_current_line(53, ng0); + t3 = ((char*)((ng1))); + t4 = (t0 + 1608); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + xsi_set_current_line(53, ng0); + t2 = (t0 + 2488); + xsi_process_wait(t2, 10000LL); + *((char **)t1) = &&LAB8; + goto LAB1; + +LAB8: xsi_set_current_line(54, ng0); + t2 = ((char*)((ng4))); + t3 = (t0 + 1448); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 8); + xsi_set_current_line(54, ng0); + t2 = (t0 + 2488); + xsi_process_wait(t2, 10000LL); + *((char **)t1) = &&LAB9; + goto LAB1; + +LAB9: xsi_set_current_line(54, ng0); + t2 = ((char*)((ng3))); + t3 = (t0 + 1608); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(54, ng0); + t2 = (t0 + 2488); + xsi_process_wait(t2, 10000LL); + *((char **)t1) = &&LAB10; + goto LAB1; + +LAB10: xsi_set_current_line(54, ng0); + t3 = ((char*)((ng1))); + t4 = (t0 + 1608); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + xsi_set_current_line(54, ng0); + t2 = (t0 + 2488); + xsi_process_wait(t2, 10000LL); + *((char **)t1) = &&LAB11; + goto LAB1; + +LAB11: xsi_set_current_line(55, ng0); + t2 = ((char*)((ng5))); + t3 = (t0 + 1448); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 8); + xsi_set_current_line(55, ng0); + t2 = (t0 + 2488); + xsi_process_wait(t2, 10000LL); + *((char **)t1) = &&LAB12; + goto LAB1; + +LAB12: xsi_set_current_line(55, ng0); + t2 = ((char*)((ng3))); + t3 = (t0 + 1608); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(55, ng0); + t2 = (t0 + 2488); + xsi_process_wait(t2, 10000LL); + *((char **)t1) = &&LAB13; + goto LAB1; + +LAB13: xsi_set_current_line(55, ng0); + t3 = ((char*)((ng1))); + t4 = (t0 + 1608); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + xsi_set_current_line(55, ng0); + t2 = (t0 + 2488); + xsi_process_wait(t2, 10000LL); + *((char **)t1) = &&LAB14; + goto LAB1; + +LAB14: xsi_set_current_line(56, ng0); + t2 = ((char*)((ng6))); + t3 = (t0 + 1448); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 8); + xsi_set_current_line(56, ng0); + t2 = (t0 + 2488); + xsi_process_wait(t2, 10000LL); + *((char **)t1) = &&LAB15; + goto LAB1; + +LAB15: xsi_set_current_line(56, ng0); + t2 = ((char*)((ng3))); + t3 = (t0 + 1608); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(56, ng0); + t2 = (t0 + 2488); + xsi_process_wait(t2, 10000LL); + *((char **)t1) = &&LAB16; + goto LAB1; + +LAB16: xsi_set_current_line(56, ng0); + t3 = ((char*)((ng1))); + t4 = (t0 + 1608); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + xsi_set_current_line(56, ng0); + t2 = (t0 + 2488); + xsi_process_wait(t2, 10000LL); + *((char **)t1) = &&LAB17; + goto LAB1; + +LAB17: goto LAB1; + +} + + +extern void work_m_11346574241544900769_1316107190_init() +{ + static char *pe[] = {(void *)Initial_43_0}; + xsi_register_didat("work_m_11346574241544900769_1316107190", "isim/TEST_FirFilter_isim_beh.exe.sim/work/m_11346574241544900769_1316107190.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_11346574241544900769_1316107190.didat b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_11346574241544900769_1316107190.didat Binary files differnew file mode 100644 index 0000000..3d1aa8f --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_11346574241544900769_1316107190.didat diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_11346574241544900769_1316107190.lin64.o b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_11346574241544900769_1316107190.lin64.o Binary files differnew file mode 100644 index 0000000..b5f34be --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_11346574241544900769_1316107190.lin64.o diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c new file mode 100644 index 0000000..68e1c8d --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c @@ -0,0 +1,337 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/verilog/src/glbl.v"; +static unsigned int ng1[] = {1U, 0U}; +static unsigned int ng2[] = {0U, 0U}; + + + +static void NetDecl_16_0(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + unsigned int t8; + unsigned int t9; + char *t10; + unsigned int t11; + unsigned int t12; + char *t13; + unsigned int t14; + unsigned int t15; + char *t16; + +LAB0: t1 = (t0 + 6952U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(16, ng0); + t2 = (t0 + 1960U); + t3 = *((char **)t2); + t2 = (t0 + 8640); + t4 = (t2 + 56U); + t5 = *((char **)t4); + t6 = (t5 + 56U); + t7 = *((char **)t6); + memset(t7, 0, 8); + t8 = 1U; + t9 = t8; + t10 = (t3 + 4); + t11 = *((unsigned int *)t3); + t8 = (t8 & t11); + t12 = *((unsigned int *)t10); + t9 = (t9 & t12); + t13 = (t7 + 4); + t14 = *((unsigned int *)t7); + *((unsigned int *)t7) = (t14 | t8); + t15 = *((unsigned int *)t13); + *((unsigned int *)t13) = (t15 | t9); + xsi_driver_vfirst_trans(t2, 0, 0U); + t16 = (t0 + 8512); + *((int *)t16) = 1; + +LAB1: return; +} + +static void Cont_48_1(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7200U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(48, ng0); + t2 = (t0 + 3640); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8704); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8528); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Cont_49_2(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7448U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(49, ng0); + t2 = (t0 + 3800); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8768); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8544); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Cont_50_3(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7696U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(50, ng0); + t2 = (t0 + 3960); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8832); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8560); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Initial_52_4(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + +LAB0: t1 = (t0 + 7944U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(52, ng0); + +LAB4: xsi_set_current_line(53, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3640); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(54, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3960); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(55, ng0); + t2 = (t0 + 7752); + xsi_process_wait(t2, 100000LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(56, ng0); + t3 = ((char*)((ng2))); + t4 = (t0 + 3640); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + xsi_set_current_line(57, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 3960); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + goto LAB1; + +} + +static void Initial_60_5(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + +LAB0: t1 = (t0 + 8192U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(60, ng0); + +LAB4: xsi_set_current_line(61, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3800); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(62, ng0); + t2 = (t0 + 8000); + xsi_process_wait(t2, 0LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(63, ng0); + t3 = ((char*)((ng2))); + t4 = (t0 + 3800); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + goto LAB1; + +} + + +extern void work_m_16541823861846354283_2073120511_init() +{ + static char *pe[] = {(void *)NetDecl_16_0,(void *)Cont_48_1,(void *)Cont_49_2,(void *)Cont_50_3,(void *)Initial_52_4,(void *)Initial_60_5}; + xsi_register_didat("work_m_16541823861846354283_2073120511", "isim/TEST_FirFilter_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat Binary files differnew file mode 100644 index 0000000..7332996 --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat diff --git a/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o Binary files differnew file mode 100644 index 0000000..718e29b --- /dev/null +++ b/isim/TEST_FirFilter_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o diff --git a/isim/isim_usage_statistics.html b/isim/isim_usage_statistics.html new file mode 100644 index 0000000..e0fd1eb --- /dev/null +++ b/isim/isim_usage_statistics.html @@ -0,0 +1,16 @@ +<TABLE BORDER CELLSPACING=0 WIDTH='100%'> +<xtag-section name="ISimStatistics"> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR> +<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value></xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>1640 ms, 393012 KB</xtag-isim-property-value></TD></TR> + +<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>17</xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>39</xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>3</xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>13</xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.06 sec, 255717 KB</xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR> +</xtag-section> +</TABLE> diff --git a/isim/lockfile b/isim/lockfile new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/isim/lockfile diff --git a/isim/pn_info b/isim/pn_info new file mode 100644 index 0000000..c5644b4 --- /dev/null +++ b/isim/pn_info @@ -0,0 +1 @@ +13.4 diff --git a/isim/work/@f@i@r@filter.sdb b/isim/work/@f@i@r@filter.sdb Binary files differnew file mode 100644 index 0000000..3618458 --- /dev/null +++ b/isim/work/@f@i@r@filter.sdb diff --git a/isim/work/@t@e@s@t_@fir@filter.sdb b/isim/work/@t@e@s@t_@fir@filter.sdb Binary files differnew file mode 100644 index 0000000..fc38cbc --- /dev/null +++ b/isim/work/@t@e@s@t_@fir@filter.sdb diff --git a/isim/work/glbl.sdb b/isim/work/glbl.sdb Binary files differnew file mode 100644 index 0000000..d34b949 --- /dev/null +++ b/isim/work/glbl.sdb @@ -21,8 +21,96 @@ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="lab5.xise"/>
- <files xmlns="http://www.xilinx.com/XMLSchema"/>
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="TEST_Bin2BCD_isim_beh.exe"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="TEST_DisplayController_isim_beh.exe"/>
+ <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="TEST_FirFilter_beh.prj"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="TEST_FirFilter_isim_beh.exe"/>
+ <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="TEST_FirFilter_isim_beh.wdb"/>
+ <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
+ <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
+ </files>
- <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">
+ <transform xil_pn:end_ts="1333048801" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1333048801">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1333049488" xil_pn:in_ck="2732522951227592992" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333049488">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="InputChanged"/>
+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="Bin2BCD.v"/>
+ <outfile xil_pn:name="ClockDivider.v"/>
+ <outfile xil_pn:name="DisplayController.v"/>
+ <outfile xil_pn:name="FIRController.v"/>
+ <outfile xil_pn:name="FIRFilter.v"/>
+ <outfile xil_pn:name="SevSegDisp.v"/>
+ <outfile xil_pn:name="TEST_Bin2BCD.v"/>
+ <outfile xil_pn:name="TEST_DisplayController.v"/>
+ <outfile xil_pn:name="TEST_FirFilter.v"/>
+ </transform>
+ <transform xil_pn:end_ts="1333049488" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8794436030188559171" xil_pn:start_ts="1333049488">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1333049488" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5025297475059373691" xil_pn:start_ts="1333049488">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1333048801" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="2765485881546830441" xil_pn:start_ts="1333048801">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1333049488" xil_pn:in_ck="2732522951227592992" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333049488">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="InputChanged"/>
+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="Bin2BCD.v"/>
+ <outfile xil_pn:name="ClockDivider.v"/>
+ <outfile xil_pn:name="DisplayController.v"/>
+ <outfile xil_pn:name="FIRController.v"/>
+ <outfile xil_pn:name="FIRFilter.v"/>
+ <outfile xil_pn:name="SevSegDisp.v"/>
+ <outfile xil_pn:name="TEST_Bin2BCD.v"/>
+ <outfile xil_pn:name="TEST_DisplayController.v"/>
+ <outfile xil_pn:name="TEST_FirFilter.v"/>
+ </transform>
+ <transform xil_pn:end_ts="1333049490" xil_pn:in_ck="2732522951227592992" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6294440187011869753" xil_pn:start_ts="1333049488">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="InputChanged"/>
+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="TEST_FirFilter_beh.prj"/>
+ <outfile xil_pn:name="TEST_FirFilter_isim_beh.exe"/>
+ <outfile xil_pn:name="fuse.log"/>
+ <outfile xil_pn:name="isim"/>
+ <outfile xil_pn:name="isim.log"/>
+ <outfile xil_pn:name="xilinxsim.ini"/>
+ </transform>
+ <transform xil_pn:end_ts="1333049490" xil_pn:in_ck="-4992000523088231073" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4694054843649941820" xil_pn:start_ts="1333049490">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="TEST_FirFilter_isim_beh.wdb"/>
+ <outfile xil_pn:name="isim.cmd"/>
+ <outfile xil_pn:name="isim.log"/>
+ </transform>
+ </transforms>
</generated_project>
@@ -16,36 +16,52 @@ <files> <file xil_pn:name="FIRController.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/> </file> <file xil_pn:name="DisplayController.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/> </file> <file xil_pn:name="SevSegDisp.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/> </file> <file xil_pn:name="ClockDivider.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/> </file> <file xil_pn:name="FIRFilter.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/> </file> <file xil_pn:name="Bin2BCD.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/> </file> + <file xil_pn:name="TEST_DisplayController.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/> + </file> + <file xil_pn:name="TEST_Bin2BCD.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="15"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="15"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="15"/> + </file> + <file xil_pn:name="TEST_FirFilter.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> + <association xil_pn:name="PostMapSimulation" xil_pn:seqID="20"/> + <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="20"/> + <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="20"/> + </file> </files> <properties> <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> @@ -59,8 +75,6 @@ <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/> - <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/> <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> @@ -77,55 +91,45 @@ <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> - <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/> - <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/> <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/> - <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/> <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> <property xil_pn:name="Device" xil_pn:value="xc6slx16" xil_pn:valueState="non-default"/> <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/> <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> - <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/> - <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/> <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/> @@ -133,12 +137,10 @@ <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/> - <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/> <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/> <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/> <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/> - <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/> <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/> @@ -165,12 +167,9 @@ <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> - <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> - <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> - <property xil_pn:name="ICAP Select" xil_pn:value="Top" xil_pn:valueState="default"/> <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> @@ -188,7 +187,6 @@ <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> - <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/> <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> @@ -209,7 +207,6 @@ <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/> - <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/> <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/> <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> @@ -221,7 +218,6 @@ <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/> <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/> - <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/> <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> @@ -252,7 +248,6 @@ <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> @@ -260,9 +255,7 @@ <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="FIRController_timesim.v" xil_pn:valueState="default"/> <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="FIRController_synthesis.v" xil_pn:valueState="default"/> <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="FIRController_translate.v" xil_pn:valueState="default"/> - <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> - <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> @@ -280,7 +273,6 @@ <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/> - <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/> <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> @@ -305,20 +297,18 @@ <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> - <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/TEST_FirFilter" xil_pn:valueState="non-default"/> + <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.TEST_FirFilter" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> - <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/> - <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/> <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> @@ -328,13 +318,11 @@ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.TEST_FirFilter" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> - <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/> - <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> @@ -359,35 +347,28 @@ <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> - <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/> <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> - <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/> <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> - <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/> - <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/> <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> <!-- --> <!-- The following properties are for internal use only. These should not be modified.--> <!-- --> - <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|TEST_FirFilter" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="lab5" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> diff --git a/xilinxsim.ini b/xilinxsim.ini new file mode 100644 index 0000000..600496d --- /dev/null +++ b/xilinxsim.ini @@ -0,0 +1 @@ +work=isim/work |