lab6HEADmaster

1 files changed, 47 insertions, 0 deletions

diff --git a/ClockDivider.v b/ClockDivider.v
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:24:11 03/16/2012 
+// Design Name: 
+// Module Name:    ClockDivider 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module ClockDivider(
+    input clk_in,
+    input rst,
+	 input [23:0] count,
+    output clk_out
+    );
+	 
+reg clk_out = 0;
+reg [23:0] c = 0;
+
+always @(posedge clk_in or posedge rst) begin
+	if (rst == 1) begin
+		c = 0;
+		clk_out = 0;
+	end else if (c == count) begin
+		clk_out = ~clk_out;
+		c = 0;
+	end else begin
+		c = c + 24'd1;
+	end
+	
+	
+end
+
+
+
+endmodule