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diff --git a/verilog/mux_2to1.v b/verilog/mux_2to1.v
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    13:02:11 10/05/2012 
+// Design Name: 
+// Module Name:    mux_2to1 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mux_2to1(
+    output out,
+    input sel,
+    input o0,
+    input o1
+    );
+
+wire a1, a2, n;
+not n1(n, sel);
+and ag1(a1, o0, n);
+and ag2(a2, o1, sel);
+or og1(out, a1, a2);
+
+endmodule