make git repoHEADmaster

24 files changed, 1359 insertions, 0 deletions

diff --git a/verilog/DFF.v b/verilog/DFF.v
new file mode 100755
index 0000000..53ae504
--- /dev/null
+++ b/verilog/DFF.v
@@ -0,0 +1,27 @@
+//D Flip-flop

+module DFF(D,     // DFF Input
+           Q,     // DFF Output
+			  Write, // Only accept input when this is set
+			  Reset, // Synchronous Reset
+			  Clk);  // Clock

+
+	//-------------Input Ports-----------------------------

+	input D;
+	input Write;

+	input Reset;
+	input Clk;
+	//-------------Output Ports----------------------------
+	output Q;

+	//-------------Wires-----------------------------------
+	//-------------Other-----------------------------------
+	reg data;
+	//------------Code Starts Here-------------------------
+	assign Q= data;
+	always @ (posedge Clk)
+	if (Reset) begin
+		data <= 1'b0;
+	end  else begin
+		if(Write)
+			data <= D; 
+	end

+endmodule

diff --git a/verilog/DFF_test.v b/verilog/DFF_test.v
new file mode 100755
index 0000000..9af6b50
--- /dev/null
+++ b/verilog/DFF_test.v
@@ -0,0 +1,51 @@
+`timescale 1ns / 1ps
+
+module DFF_test;
+
+	//-------------Input Ports-----------------------------
+	reg D;
+	reg Write;
+	reg Reset;
+	reg Clk;
+	//-------------Output Ports----------------------------
+	wire Q;
+	//-------------Wires-----------------------------------
+	//-------------Other-----------------------------------
+	//------------Code Starts Here-------------------------
+
+	// Instantiate the Unit UDer Test (UUT)
+	DFF uut (
+      .D(D), 
+		.Q(Q),
+		.Write(Write),
+		.Reset(Reset),
+		.Clk(Clk)
+	);
+
+	initial 
+	begin
+		$display ("time\tD\tQ\tWrite\tReset\tClk");	
+		$monitor ("%g\t%b\t%b\t%b\t%b\t%b", 
+					 $time, D, Q, Write, Reset, Clk);
+	end
+ 
+	// Test vectors
+	always begin	
+	
+		     D= 0; Write= 1; Reset= 1; Clk= 0;
+		#20  D= 0; Write= 1; Reset= 1; Clk= 1;
+		#20  D= 0; Write= 1; Reset= 0; Clk= 0;
+		#20  D= 0; Write= 1; Reset= 0; Clk= 1;
+		#20  D= 1; Write= 1; Reset= 0; Clk= 0;
+		#20  D= 1; Write= 1; Reset= 0; Clk= 1;
+		#20  D= 0; Write= 0; Reset= 0; Clk= 0;
+		#20  D= 0; Write= 0; Reset= 0; Clk= 1;
+		#20  D= 1; Write= 1; Reset= 1; Clk= 0;
+		#20  D= 1; Write= 1; Reset= 1; Clk= 1;
+		#20  D= 0; Write= 1; Reset= 0; Clk= 0;
+		
+		#20  $finish;      // Terminate simulation
+	end
+      
+endmodule
+
diff --git a/verilog/S1.v b/verilog/S1.v
new file mode 100755
index 0000000..95321b4
--- /dev/null
+++ b/verilog/S1.v
@@ -0,0 +1,67 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    20:03:20 10/21/2012 
+// Design Name: 
+// Module Name:    Stage1 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Stage1(
+	type, // R or I type
+	alu_op, // which aluoption to take
+	r1sel, // which register to write to
+	r2sel, // the value of a selected register
+	r3sel, // the value of another seclected register
+	imm, // the value if it's an immediate
+	
+	instr, // the instruction to run
+	clk, // clock input
+	reset // rest everything
+);
+parameter BITS = 32; // width of reg select
+parameter RSELW = 5; // N-BIT Values
+parameter DEPTH = 3; // pipeline depth
+
+output type;
+output [2:0] alu_op; // always 3 bits
+output [RSELW-1:0] r1sel;
+output [RSELW-1:0] r2sel, r3sel;
+output [15:0] imm; // 32 bit opcode -> 16 bit immediate
+input [31:0] instr; // 32 bit opcode
+input clk;
+input reset;
+
+
+wire [31:0] iw;
+nbit_reg #(32) ireg(
+	.nD(instr),
+	.nQ(iw),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+
+instruction_decode dec(
+	.op_type(type),
+	.alu_op(alu_op),
+	.r1sel(r1sel),
+	.r2sel(r2sel),
+	.r3sel(r3sel),
+	.immediate(imm),
+	.instruction(iw)
+);
+
+
+endmodule
diff --git a/verilog/S2.v b/verilog/S2.v
new file mode 100755
index 0000000..5c142b3
--- /dev/null
+++ b/verilog/S2.v
@@ -0,0 +1,116 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    23:49:19 10/21/2012 
+// Design Name: 
+// Module Name:    Stage2 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Stage2(
+	operand1,
+	operand2,
+	wout,
+	alu_op_out,
+	op_type, // R or I instruction
+	alu_op_in,
+	data1,
+	data2,
+	immediate,
+	win,
+	clk,
+	reset
+);
+
+parameter BITS=32;
+parameter RSELW=5;
+
+output [BITS-1:0] operand1, operand2;
+output [2:0] alu_op_out;
+output [RSELW-1:0] wout;
+input op_type;
+input [2:0] alu_op_in;
+input [BITS-1:0] data1, data2;
+input [15:0] immediate;
+input [RSELW-1:0] win;
+input clk, reset;
+
+
+wire [BITS-1:16] sign_extend = immediate[15] ? ~0 : 0;
+wire [BITS-1:0] immw;
+assign immw = {sign_extend,immediate};
+
+wire [BITS-1:0] op2w;
+
+nbit_reg #(BITS) o1reg(
+	.nD(data1),
+	.nQ(operand1),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+
+wire [BITS-1:0] d2wo, imw0;
+nbit_reg #(BITS) o2reg(
+	.nD(data2),
+	.nQ(d2wo),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+
+nbit_reg #(BITS) imreg(
+	.nD(immw),
+	.nQ(imw0),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+
+nbit_reg #(3) opreg(
+	.nD(alu_op_in),
+	.nQ(alu_op_out),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+
+nbit_reg #(RSELW) wreg(
+	.nD(win),
+	.nQ(wout),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+
+nbit_reg #(1) treg(
+	.nD(op_type),
+	.nQ(op_typew),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+
+generate 
+genvar i;
+for (i = 0; i < BITS; i = i + 1) begin:mux
+	nbit_mux#(1) mux(
+		.MuxIn({imw0[i],d2wo[i]}),
+		.MuxOut(operand2[i]),
+		.MuxSel(op_typew)
+	);
+end
+endgenerate
+
+endmodule
diff --git a/verilog/S3.v b/verilog/S3.v
new file mode 100755
index 0000000..2fa74ef
--- /dev/null
+++ b/verilog/S3.v
@@ -0,0 +1,53 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    02:50:52 10/22/2012 
+// Design Name: 
+// Module Name:    Stage3 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Stage3(
+	alu_in,
+	wsel_in,
+	alu_out,
+	wsel_out,
+	clk,
+	reset
+    );
+parameter BITS=32;
+parameter RSELW=5;
+input clk, reset;
+input [BITS-1:0] alu_in;
+input [RSELW-1:0] wsel_in;
+
+output [BITS-1:0] alu_out;
+output [RSELW-1:0] wsel_out;
+
+nbit_reg #(BITS) rreg(
+	.nD(alu_in),
+	.nQ(alu_out),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+
+nbit_reg #(RSELW) wreg(
+	.nD(wsel_in),
+	.nQ(wsel_out),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+endmodule
diff --git a/verilog/alu.v b/verilog/alu.v
new file mode 100755
index 0000000..158d9a6
--- /dev/null
+++ b/verilog/alu.v
@@ -0,0 +1,67 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    19:56:04 10/03/2012 
+// Design Name: 
+// Module Name:    alu 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module alu( r1, r2, r3, aluop);
+
+parameter BITS = 32;
+
+input [BITS-1:0] r2, r3;
+input [2:0] aluop;
+output [BITS-1:0] r1;
+
+wire cinw;
+wire carries [0:BITS-1];
+wire [BITS-1:0] r1out;
+cin_choice cin(cinw, aluop);
+
+alu_slice1bit alu_slice_init(
+				.r1(r1out[0]), 
+				.cout(carries[0]),
+				.r2(r2[0]),
+				.r3(r3[0]),
+				.cin(cinw),
+				.op(aluop)
+			);
+
+generate
+	genvar i;
+	for (i = 1; i < BITS; i = i + 1) begin:aluslice
+		alu_slice1bit alu_slice(
+					.r1(r1out[i]), 
+					.cout(carries[i]),
+					.r2(r2[i]),
+					.r3(r3[i]),
+					.cin(carries[i-1]),
+					.op(aluop)
+				);
+	end
+endgenerate
+
+wire sltw;
+slt sltg(sltw, r2[BITS-1], r3[BITS-1], r1out[BITS-1], carries[BITS-1]);
+
+
+wire doslt;
+wire [BITS-2:0] s;
+assign s = 0;
+and a(doslt, aluop[2], aluop[1], aluop[0]);
+mux_2to1_nbit #(BITS) m(r1, doslt, r1out, {s,sltw});
+
+endmodule
diff --git a/verilog/alu_slice1bit.v b/verilog/alu_slice1bit.v
new file mode 100755
index 0000000..7f481d1
--- /dev/null
+++ b/verilog/alu_slice1bit.v
@@ -0,0 +1,65 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    12:08:08 10/04/2012 
+// Design Name: 
+// Module Name:    alu_slice1bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module alu_slice1bit(
+    output r1,
+    output cout,
+    input r2,
+    input r3,
+    input cin,
+    input [2:0] op
+    );
+
+// wires for operation outputs and carries
+wire movw, notw, notw2, addw, addcw, subw, subcw, orw, andw, xorw, sltw, sltcw;
+
+not notg(notw, r2); // NOT: R1 = ~R2
+
+not nogt(notw2, r3);                  // for subtract; higher level sets cin to 1
+fa addg(addw, addcw, r2, r3, cin);    // ADD: R1 = R2 + R3
+fa subg(subw, subcw, r2, notw2, cin); // SUB: R1 = R2 - R3
+
+or org(orw, r2, r3);           // OR:  R1 = R2 | R3
+and andg(andw, r2, r3);        // AND: R1 = R2 & R3
+xor_custom xorg(xorw, r2, r3); // XOR: R1 = R2 ^ R3
+
+mux_8to1 opsel( .out(r1),
+					 .sel(op),
+					 .o0(r2),
+					 .o1(notw),
+					 .o2(addw),
+					 .o3(subw),
+					 .o4(orw),
+					 .o5(andw),
+					 .o6(xorw),
+					 .o7(subw)
+				);
+				
+mux_8to1 csel( .out(cout),
+					.sel(op),
+					.o0(1'b0), .o1(1'b0),
+					.o2(addcw),
+					.o3(subcw),
+					.o4(1'b0), .o5(1'b0),
+					.o6(1'b0),
+					.o7(subcw) 
+				);
+
+endmodule
diff --git a/verilog/cin_choice.v b/verilog/cin_choice.v
new file mode 100755
index 0000000..e6ab92b
--- /dev/null
+++ b/verilog/cin_choice.v
@@ -0,0 +1,39 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    12:44:24 10/04/2012 
+// Design Name: 
+// Module Name:    cin_choice 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module cin_choice(
+    output cin,
+    input [2:0] op
+    );
+
+// we only want non-zero cin if we're subtracting.
+// Subtraction is used in both sub and slt, so we have two cases
+// 011 and 111. output is 1 for these and 0 for others 
+
+// This is equivalent to a'bc + abc (where a, b, c are bits in op)
+
+wire notw, subw, sltw;
+not n1(notw, op[2]);
+
+and sub_choose(subw, notw, op[1], op[0]);
+and slt_choose(sltw, op[2], op[1], op[0]);
+or choose(cin, sltw, subw);
+
+endmodule
diff --git a/verilog/clock_delay.v b/verilog/clock_delay.v
new file mode 100755
index 0000000..048b8ef
--- /dev/null
+++ b/verilog/clock_delay.v
@@ -0,0 +1,52 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    22:02:54 10/21/2012 
+// Design Name: 
+// Module Name:    clock_delay 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module clock_delay(
+     out,
+     in,
+	  clk,
+	  reset
+    );
+
+input clk, reset;
+
+parameter TIME=3; // number of bits to save
+parameter BITS=5; // number of bits per tick
+
+input [BITS-1:0] in;
+output [BITS-1:0] out;
+
+wire [BITS-1:0] connector [0:TIME+1];
+
+assign connector[0] = in;
+assign out = connector[TIME+1];
+
+
+generate 
+genvar i;
+
+for (i = 1; i <= TIME+1; i = i + 1) begin:reggen
+	nbit_reg #(BITS) nb(.nD(connector[i-1]), .nQ(connector[i]), .Write(1'b1), .Reset(reset), .Clk(clk));
+end
+
+endgenerate
+
+
+endmodule
diff --git a/verilog/datapath.v b/verilog/datapath.v
new file mode 100755
index 0000000..beef5d9
--- /dev/null
+++ b/verilog/datapath.v
@@ -0,0 +1,101 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    23:27:42 10/21/2012 
+// Design Name: 
+// Module Name:    datapath 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module datapath(
+     aluout, // the output from the alu
+     instruction, // the instruction to execute
+	  clk,
+	  reset
+    );
+input clk, reset;
+	 
+parameter BITS = 32; // size of ALU operations and registers
+parameter RSELW = 5; // bits required to select a register
+parameter DEPTH = 3; // pipeline depth
+
+input [31:0] instruction;
+output [BITS-1:0] aluout;
+
+wire [RSELW-1:0] rsel1, rsel2; // read selectors
+wire [RSELW-1:0] wsel, wsel1, wsel2; // write selectors
+wire [2:0] alu_op;
+wire [15:0] immediate;
+
+// stage 1 handles decoding and register file select signals
+Stage1 #(BITS,RSELW,DEPTH) s1(
+	.type(op_type),
+	.alu_op(alu_op),
+	.r1sel(wsel1),
+	.r2sel(rsel1),
+	.r3sel(rsel2),
+	.imm(immediate),
+	.instr(instruction),
+	.clk(clk),
+	.reset(reset)
+);
+
+// the registers
+wire [BITS-1:0] data1, data2;
+nbit_register_file #(RSELW,BITS) regfile(
+	.WriteData(aluout),
+	.ReadData1(data1),
+	.ReadData2(data2),
+	.ReadSelect1(rsel1),
+	.ReadSelect2(rsel2),
+	.WriteSelect(wsel[RSELW-1:0]),
+	.WriteEnable(1'b1),
+	.Reset(reset),
+	.Clk(clk)
+);
+
+wire [BITS-1:0] operand1, operand2;
+wire [2:0] alu_op_out;
+Stage2 #(BITS, RSELW) s2(
+	.operand1(operand1),
+	.operand2(operand2),
+	.wout(wsel2),
+	.alu_op_out(alu_op_out),
+	.op_type(op_type),
+	.alu_op_in(alu_op),
+	.data1(data1),
+	.data2(data2),
+	.immediate(immediate),
+	.win(wsel1),
+	.clk(clk),
+	.reset(reset)
+);
+
+wire [BITS-1:0] alu_result;
+alu #(BITS) a(
+	.r1(alu_result),
+	.r2(operand1),
+	.r3(operand2),
+	.aluop(alu_op_out)
+);
+
+Stage3 #(BITS,RSELW) s3(
+	.alu_in(alu_result),
+	.alu_out(aluout),
+	.wsel_in(wsel2),
+	.wsel_out(wsel),
+	.clk(clk),
+	.reset(reset)
+);
+endmodule
diff --git a/verilog/full_adder.v b/verilog/full_adder.v
new file mode 100755
index 0000000..c669c6a
--- /dev/null
+++ b/verilog/full_adder.v
@@ -0,0 +1,61 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    12:24:15 10/04/2012 
+// Design Name: 
+// Module Name:    fa 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module fa(
+    output sum,
+    output cout,
+    input a,
+    input b,
+    input cin
+    );
+
+
+wire s1, s2, s3, s4; // sum wires
+wire c1, c2, c3; // carry wires
+wire ia, ib, ic; // inverted wires
+
+// invert wires ad needed for the sum
+not n1(ia, a);
+not n2(ib, b);
+not n3(ic, cin);
+
+// SUM CALCULATION
+
+// compute relevant minterms
+and a1(s1, ia, ib, cin);
+and a2(s2, ia, b, ic);
+and a3(s3, a, ib, ic);
+and a4(s4, a, b, cin);
+
+// or minterm results
+or o1(sum, s1, s2, s3, s4);
+
+// CARRY CALCULATION
+
+// compute minterms
+and ca1(c1, a, b);
+and ca2(c2, a, cin);
+and ca3(c3, b, cin);
+
+// or results
+or o2(cout, c1, c2, c3); 
+
+
+endmodule
diff --git a/verilog/instruction_decode.v b/verilog/instruction_decode.v
new file mode 100755
index 0000000..f74e466
--- /dev/null
+++ b/verilog/instruction_decode.v
@@ -0,0 +1,41 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    20:27:39 10/21/2012 
+// Design Name: 
+// Module Name:    instruction_decode 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module instruction_decode(
+    output op_type,
+    output math_type,
+    output [2:0] alu_op,
+    output [4:0] r1sel,
+    output [4:0] r2sel,
+    output [4:0] r3sel,
+    output [15:0] immediate,
+    input [31:0] instruction
+);
+
+
+assign math_type = instruction[30];
+assign op_type = instruction[29];
+assign alu_op = instruction[28:26];
+assign r1sel = instruction[25:21];
+assign r2sel = instruction[20:16];
+assign r3sel = instruction[15:11];
+assign immediate = instruction[15:0];
+
+endmodule
diff --git a/verilog/mux_2to1.v b/verilog/mux_2to1.v
new file mode 100755
index 0000000..48ad684
--- /dev/null
+++ b/verilog/mux_2to1.v
@@ -0,0 +1,34 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    13:02:11 10/05/2012 
+// Design Name: 
+// Module Name:    mux_2to1 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mux_2to1(
+    output out,
+    input sel,
+    input o0,
+    input o1
+    );
+
+wire a1, a2, n;
+not n1(n, sel);
+and ag1(a1, o0, n);
+and ag2(a2, o1, sel);
+or og1(out, a1, a2);
+
+endmodule
diff --git a/verilog/mux_2to1_nbit.v b/verilog/mux_2to1_nbit.v
new file mode 100755
index 0000000..3e70955
--- /dev/null
+++ b/verilog/mux_2to1_nbit.v
@@ -0,0 +1,39 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    13:03:36 10/05/2012 
+// Design Name: 
+// Module Name:    mux_2to1_nbit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mux_2to1_nbit(
+     out,
+     sel,
+     o0,
+     o1
+    );
+parameter BITS = 32;
+input [BITS-1:0] o1, o0;
+output [BITS-1:0] out;
+input sel;
+
+generate
+genvar i;
+	for (i = 0; i < BITS; i = i + 1) begin:muxgen
+		mux_2to1 m(out[i], sel, o0[i], o1[i]);
+	end
+endgenerate
+
+endmodule
diff --git a/verilog/mux_8to1.v b/verilog/mux_8to1.v
new file mode 100755
index 0000000..f9ebb65
--- /dev/null
+++ b/verilog/mux_8to1.v
@@ -0,0 +1,55 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    22:40:54 10/04/2012 
+// Design Name: 
+// Module Name:    mux_8to1 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mux_8to1(
+			output out,
+			input [2:0] sel,
+			input o0,
+			input o1,
+			input o2,
+			input o3,
+			input o4,
+			input o5,
+			input o6,
+			input o7
+    );
+
+wire sn0, sn1, sn2;
+not n1(sn0, sel[0]);
+not n2(sn1, sel[1]);
+not n3(sn2, sel[2]);
+wire a0, a1, a2, a3, a4, a5, a6, a7;
+
+// 111 corresponds to ag0
+
+and ag0(a0, sn2, sn1, sn0, o0);
+and ag1(a1, sn2, sn1, sel[0], o1);
+and ag2(a2, sn2, sel[1], sn0, o2);
+and ag3(a3, sn2, sel[1], sel[0], o3);
+
+and ag4(a4, sel[2], sn1, sn0, o4);
+and ag5(a5, sel[2], sn1, sel[0], o5);
+and ag6(a6, sel[2], sel[1], sn0, o6);
+and ag7(a7, sel[2], sel[1], sel[0], o7);
+
+or(out, a0, a1, a2, a3, a4, a5, a6, a7);
+
+
+endmodule
diff --git a/verilog/nbit_demux.v b/verilog/nbit_demux.v
new file mode 100755
index 0000000..5be44c8
--- /dev/null
+++ b/verilog/nbit_demux.v
@@ -0,0 +1,33 @@
+//n bit DeMux
+// Specify the number of select lines as a parameter.

+module nbit_demux(DeMuxIn,   // DeMux input: 1 bit.
+                  DeMuxOut,  // DeMux output: 2^SELECT_WIDTH bits.
+						DeMuxSel); // DeMux select lines: SELECT_WIDTH bits.
+
+// Specifies the select line width.
+parameter SELECT_WIDTH = 3;
+
+//-------------Input Ports-----------------------------
+input  DeMuxIn;
+input  [SELECT_WIDTH-1:0] DeMuxSel;
+//-------------Output Ports----------------------------
+output [2 ** SELECT_WIDTH-1:0] DeMuxOut;
+//-------------Wires-----------------------------------
+wire [2 ** SELECT_WIDTH-1:0] select;
+//-------------Other-----------------------------------
+//------------Code Starts Here-------------------------
+
+generate
+	genvar i; // Instance variable
+	
+	// address decoder
+	assign select[2 ** SELECT_WIDTH-1:0] = 2 ** DeMuxSel[SELECT_WIDTH-1:0];
+	
+	// Generation for loop
+	for(i= 0;i< 2 ** SELECT_WIDTH;i= i+1)
+	begin:demux_loop
+		assign DeMuxOut[i] = DeMuxIn & select[i];
+	end	
+endgenerate
+

+endmodule

diff --git a/verilog/nbit_mux.v b/verilog/nbit_mux.v
new file mode 100755
index 0000000..fb5cd14
--- /dev/null
+++ b/verilog/nbit_mux.v
@@ -0,0 +1,19 @@
+//n bit Mux
+// Specify the number of select lines as a parameter.

+module nbit_mux(MuxIn,   // Mux input: 2^SELECT_WIDTH bits.
+                MuxOut,  // Mux output: 1 bit.
+					 MuxSel); // Mux select lines: SELECT_WIDTH bits.
+
+// Specifies the select line width.
+parameter SELECT_WIDTH = 3;
+
+//-------------Input Ports-----------------------------
+input  [2 ** SELECT_WIDTH-1:0] MuxIn;
+input  [SELECT_WIDTH-1:0] MuxSel;
+//-------------Output Ports----------------------------
+output MuxOut;
+//-------------Wires-----------------------------------
+//-------------Other-----------------------------------
+//------------Code Starts Here-------------------------
+assign MuxOut = MuxIn[MuxSel];

+endmodule

diff --git a/verilog/nbit_reg.v b/verilog/nbit_reg.v
new file mode 100755
index 0000000..892d42c
--- /dev/null
+++ b/verilog/nbit_reg.v
@@ -0,0 +1,23 @@
+//n bit register

+

+module nbit_reg(nD,    // Register Input
+                nQ,    // Register Output
+					 Write, // Only accept input when this is set
+					 Reset, // Synchronous Reset
+					 Clk);  // Clock
+
+// Specifies the register data width.
+parameter DATA_WIDTH = 32;
+	
+//-------------Input Ports-----------------------------
+input [DATA_WIDTH-1:0] nD;
+input Write;
+input Reset;
+input Clk;
+//-------------Output Ports----------------------------
+output [DATA_WIDTH-1:0] nQ;
+//-------------Wires-----------------------------------
+//-------------Other-----------------------------------
+//------------Code Starts Here-------------------------
+DFF DFFs[DATA_WIDTH-1:0] (nD, nQ, Write, Reset, Clk);

+endmodule

diff --git a/verilog/nbit_register_file.v b/verilog/nbit_register_file.v
new file mode 100755
index 0000000..8711209
--- /dev/null
+++ b/verilog/nbit_register_file.v
@@ -0,0 +1,76 @@
+// nbit_register_file
+//
+// A generic register file which can be parameterized
+// by the following:
+//
+// - number of register select lines REG_SELECT_WIDTH: 
+//   number of registers in the file is 2 to the power 
+//   of this number.
+//
+// - number of register bits DATA_WIDTH.
+//
+// Updates:
+// 10/18: Reset fix.
+// 10/21: Timing fix.
+//

+module nbit_register_file(WriteData,   // Input data
+                          ReadData1,   // Output data 1
+                          ReadData2,   // Output data 2
+                          ReadSelect1, // Select lines for output 1
+                          ReadSelect2, // Select lines for output 2
+                          WriteSelect, // Select lines for input
+                          WriteEnable, // Causes write to take place on posedge
+                          Reset,       // Synchronous reset
+                          Clk);        // Clock
+
+// Register select line size (number of registers is 2 
+// to the power of this number).
+parameter REG_SELECT_WIDTH = 1;
+// Register size in bits.
+parameter DATA_WIDTH = 32;
+
+//-------------Input Ports-----------------------------
+input [DATA_WIDTH-1:0]       WriteData;
+input [REG_SELECT_WIDTH-1:0] ReadSelect1;
+input [REG_SELECT_WIDTH-1:0] ReadSelect2;
+input [REG_SELECT_WIDTH-1:0] WriteSelect;
+input WriteEnable;
+input Reset;
+input Clk;
+//-------------Output Ports----------------------------
+output [DATA_WIDTH-1:0] ReadData1;
+output [DATA_WIDTH-1:0] ReadData2;
+//-------------Wires-----------------------------------
+wire [2 ** REG_SELECT_WIDTH-1:0] w_reg_to_outmux [DATA_WIDTH-1:0];
+wire [2 ** REG_SELECT_WIDTH-1:0] w_write_select;
+//-------------Other-----------------------------------
+//------------Code Starts Here-------------------------
+
+// Muxes from registers to outputs
+generate
+	genvar k; // Instance variable
+	// Generation for loop
+	for(k= 0;k< DATA_WIDTH;k= k+1)
+	begin:mux_loop
+		nbit_mux #(REG_SELECT_WIDTH) nbitmuxes1 (w_reg_to_outmux[k], ReadData1[k], ReadSelect1);
+		nbit_mux #(REG_SELECT_WIDTH) nbitmuxes2 (w_reg_to_outmux[k], ReadData2[k], ReadSelect2);
+	end
+endgenerate
+
+// Demux to select which register to write to
+nbit_demux #(REG_SELECT_WIDTH) writeselect (WriteEnable, w_write_select, WriteSelect);
+
+// Array of D Flip-flops for the registers
+generate
+	genvar i,j; // Instance variable
+	// Generation for loop
+	for(i= 0;i< DATA_WIDTH;i= i+1)
+	begin:reg_loop1
+		 for(j= 0;j< 2 ** REG_SELECT_WIDTH;j= j+1)
+		 begin:reg_loop2
+			 DFF DFFS (WriteData[i],w_reg_to_outmux[i][j],w_write_select[j],Reset,Clk);
+		 end
+	end
+endgenerate
+
+endmodule
diff --git a/verilog/overflow.v b/verilog/overflow.v
new file mode 100755
index 0000000..1662d21
--- /dev/null
+++ b/verilog/overflow.v
@@ -0,0 +1,50 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    22:17:44 10/04/2012 
+// Design Name: 
+// Module Name:    overflow 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module overflow(
+    output ovf,
+    input r2,
+    input r3,
+	 input r1,
+    input carry
+    );
+
+// overflow occurs (in subtraction) only when the signs are different
+// for r2 - r3
+// if r2 is negative, and r3 is potitive, will overflow to positive
+// so cout would be 0
+// if r2 is positive and r3 is negative, will overflow to negative
+// so cout would be 1
+
+
+wire r2pos, r3pos, r1pos, nsout;
+wire aw1, aw2;
+
+not n1(r2pos, r2); // positive if not r2
+not n2(r3pos, r3); // "" "" "" r3
+not n3(r1pos, r1);
+not n4(nsout, carry); 
+
+and a1(aw1, r2, r3pos, r1pos,carry); // negative - positive = bigger negative and can overflow
+and a2(aw2, r2pos, r3, r1, nsout); // pos - neg = pos
+
+or o1(ovf, aw1, aw2);
+
+endmodule
diff --git a/verilog/slt.v b/verilog/slt.v
new file mode 100755
index 0000000..2501a07
--- /dev/null
+++ b/verilog/slt.v
@@ -0,0 +1,45 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:49:01 10/05/2012 
+// Design Name: 
+// Module Name:    slt 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module slt(
+    output out,
+    input r2,
+    input r3,
+    input signres,
+    input carryres
+    );
+
+// r2 is less than r3 if the result of subtraction is negative
+// or if it's positive and there's overflow
+
+wire ovfw, novfw, pos;
+
+overflow ovf(ovfw, r2, r3, signres, carryres);
+not n1(novfw, ovfw);
+not n2(pos, signres);
+
+wire aw1, aw2;
+
+and a1(aw1, signres, novfw);
+and a2(aw2, pos, ovfw);
+
+or o1(out, aw1, aw2);
+
+endmodule
diff --git a/verilog/test_alu.v b/verilog/test_alu.v
new file mode 100755
index 0000000..9b936ce
--- /dev/null
+++ b/verilog/test_alu.v
@@ -0,0 +1,129 @@
+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   23:34:01 10/04/2012
+// Design Name:   toplevel
+// Module Name:   /ad/eng/users/m/g/mgabed/Documents/ec413/mgabed-lab4/test_alu.v
+// Project Name:  mgabed-lab4
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: toplevel
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module test_alu;
+
+	// Inputs
+	reg [31:0] r2;
+	reg [31:0] r3;
+	reg [2:0] aluop;
+	reg reset;
+	reg clk;
+
+	// Outputs
+	wire [31:0] r1;
+
+	// Instantiate the Unit Under Test (UUT)
+	toplevel uut (
+		.r1(r1), 
+		.r2(r2), 
+		.r3(r3), 
+		.aluop(aluop), 
+		.reset(reset), 
+		.clk(clk)
+	);
+
+	initial begin
+		// Initialize Inputs
+		r2 = 0;
+		r3 = 0;
+		aluop = 0;
+		reset = 0;
+		clk = 1;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+	
+		// Add stimulus here
+		fork
+		begin
+			// test MOV
+			aluop = 3'b0;
+			r2 = 391; #2;
+			r2 = 81283; #2;
+			r3 = 3281; r2 = 1; #2;
+			r2 = 0; #2;
+			#20;
+			
+			// test NOT
+			aluop = 3'b1;
+			r2 = 391; #2;
+			r2 = 81835; #2;
+			r2 = 32'b110101011; #2;
+			#20;
+			
+			// test ADD
+			aluop = 3'b010;
+			r2 = 20; r3 = 50; #2;
+			r2 = -18; r3 = 188; #2;
+			r2 = 0; r3 = 818; #2;
+			r2 = 8184803; r3 =818501028; #2;
+			#20;
+			
+			// test SUB
+			aluop = 3'b011;
+			r2 = 180; r3 = 170; #2;
+			r2 = 50; r3 = 90; #2;
+			r2 = -50; r3 = -150; #2;
+			#20;
+			
+			// test OR
+			aluop = 3'b100;
+			r2 = 32'b01101001; r3 = 32'b10010110; #2;
+			r2 = 18581; r3 = 18204; #2;
+			#20;
+			
+			// test AND
+			aluop = 3'b101;
+			r2 = 32'b10101010; r3 = 23'b11001100; #2;
+			r2 = 8101; r2 = 192189258; #2;
+			#20;
+			
+			// test XOR
+			aluop = 3'b110;
+			r2 = 32'b11110011; r3 = 32'b11000011; #2;
+			r2 = 182381052; r3 = 19285; #2;
+			#20;
+			
+			// test SLT
+			aluop = 3'b111;
+			r2 = 500; r3 = 40; #2;
+			r2 = -5; r3 = 100; #2;
+			r2 = 1; r3 = 5; #2;
+			r2 = 32'hfffffff0; r3 = 189; #2;
+			r2 = 0; r3 = 0; #2;
+			r2 = 32'hf0000000; r3 = 32'hf0000001; #2;
+			r2 = 32'h7fffffff; r3 = 32'h80000000; #2;
+
+			#20;
+		end
+		
+		while (1) begin
+			clk = ~clk; #1;
+		end
+		join
+	end
+      
+endmodule
+
diff --git a/verilog/test_slt.v b/verilog/test_slt.v
new file mode 100755
index 0000000..4ae94c3
--- /dev/null
+++ b/verilog/test_slt.v
@@ -0,0 +1,76 @@
+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   13:25:07 10/05/2012
+// Design Name:   slt
+// Module Name:   /ad/eng/users/m/g/mgabed/Documents/ec413/mgabed-lab4/test_slt.v
+// Project Name:  mgabed-lab4
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: slt
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module test_slt;
+
+	// Inputs
+	reg r2;
+	reg r3;
+	reg signres;
+	reg carryres;
+
+	// Outputs
+	wire out;
+
+	// Instantiate the Unit Under Test (UUT)
+	slt uut (
+		.out(out), 
+		.r2(r2), 
+		.r3(r3), 
+		.signres(signres), 
+		.carryres(carryres)
+	);
+
+	initial begin
+		// Initialize Inputs
+		r2 = 0;
+		r3 = 0;
+		signres = 0;
+		carryres = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+        
+		// Add stimulus here
+		signres = 1; carryres = 1; r2 = 1; r3 = 1; #5;
+		signres = 1; carryres = 1; r2 = 1; r3 = 0; #5;
+		signres = 1; carryres = 1; r2 = 0; r3 = 1; #5;
+		signres = 1; carryres = 1; r2 = 0; r3 = 0; #5;
+		signres = 1; carryres = 0; r2 = 1; r3 = 1; #5;
+		signres = 1; carryres = 0; r2 = 1; r3 = 0; #5;
+		signres = 1; carryres = 0; r2 = 0; r3 = 1; #5;
+		signres = 1; carryres = 0; r2 = 0; r3 = 0; #5;
+		signres = 0; carryres = 1; r2 = 1; r3 = 1; #5;
+		signres = 0; carryres = 1; r2 = 1; r3 = 0; #5;
+		signres = 0; carryres = 1; r2 = 0; r3 = 1; #5;
+		signres = 0; carryres = 1; r2 = 0; r3 = 0; #5;
+		signres = 0; carryres = 0; r2 = 1; r3 = 1; #5;
+		signres = 0; carryres = 0; r2 = 1; r3 = 0; #5;
+		signres = 0; carryres = 0; r2 = 0; r3 = 1; #5;
+		signres = 0; carryres = 0; r2 = 0; r3 = 0; #5;
+
+	end
+      
+endmodule
+
diff --git a/verilog/xor.v b/verilog/xor.v
new file mode 100755
index 0000000..0282080
--- /dev/null
+++ b/verilog/xor.v
@@ -0,0 +1,40 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    12:20:45 10/04/2012 
+// Design Name: 
+// Module Name:    xor 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module xor_custom( 
+    output o,
+    input a,
+    input b
+    );
+
+wire na, nb;
+wire aw1, aw2;
+// xor (a,b) = ab' + a'b
+
+not n1(na, a);
+not n2(nb, b);
+
+and a1(aw1, a, nb);
+and a2(aw2, na, b);
+
+or o1(o, aw1, aw2);
+
+
+endmodule