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1 files changed, 39 insertions, 0 deletions

diff --git a/verilog/mux_2to1_nbit.v b/verilog/mux_2to1_nbit.v
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+++ b/verilog/mux_2to1_nbit.v
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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    13:03:36 10/05/2012 
+// Design Name: 
+// Module Name:    mux_2to1_nbit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mux_2to1_nbit(
+     out,
+     sel,
+     o0,
+     o1
+    );
+parameter BITS = 32;
+input [BITS-1:0] o1, o0;
+output [BITS-1:0] out;
+input sel;
+
+generate
+genvar i;
+	for (i = 0; i < BITS; i = i + 1) begin:muxgen
+		mux_2to1 m(out[i], sel, o0[i], o1[i]);
+	end
+endgenerate
+
+endmodule