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authorMichael Abed <michaelabed@gmail.com>2012-12-02 12:06:19 -0500
committerMichael Abed <michaelabed@gmail.com>2012-12-02 12:06:19 -0500
commitd6d76f552c28503784d9ccd26528a4d8dada18ef (patch)
tree96625c709b1a44791c0ddbc161e2753e91cdd0fb /fsm.v
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+`timescale 1ns / 1ps
+// FSM module
+//
+// drives the data path through multiple cycles
+
+module fsm(
+ output [3:0] state,
+ input [2:0] instrtype,
+ input rst,
+ input clk
+);
+
+`include "params.v"
+
+reg [3:0] state, nextstate;
+
+always @(*) begin
+ if (rst) begin
+ nextstate = FETCH;
+ end else begin
+ case (state)
+ FETCH: nextstate = DECODE;
+ DECODE: if (instrtype == IINSTR || instrtype == RINSTR)
+ nextstate = ALUOP;
+ else if (instrtype == MEMRINSTR || instrtype == MEMWINSTR)
+ nextstate = MEMCALC;
+ else if (instrtype == BRINSTR)
+ nextstate = BRANCH;
+ else if (instrtype == JINSTR)
+ nextstate = JUMP;
+ MEMCALC: if (instrtype == MEMWINSTR)
+ nextstate = MEMWRITE;
+ else if (instrtype == MEMRINSTR)
+ nextstate = MEMREAD;
+ MEMWRITE: nextstate = FETCH;
+ MEMREAD: nextstate = MEMSTORE;
+ MEMSTORE: nextstate <= FETCH;
+ ALUOP: nextstate = ALUSTORE;
+ ALUSTORE: nextstate = FETCH;
+ BRANCH: nextstate = FETCH;
+ JUMP: nextstate = FETCH;
+ endcase
+ end
+end
+
+always @(posedge clk or posedge rst) begin
+ state <= rst ? FETCH : nextstate;
+end
+
+endmodule
+