/verilog/
../
DFF.v
DFF_test.v
S1.v
S2.v
S3.v
alu.v
alu_slice1bit.v
cin_choice.v
clock_delay.v
datapath.v
full_adder.v
instruction_decode.v
mux_2to1.v
mux_2to1_nbit.v
mux_8to1.v
nbit_demux.v
nbit_mux.v
nbit_reg.v
nbit_register_file.v
overflow.v
slt.v
test_alu.v
test_slt.v
xor.v