diff options
| author | Michael Abed <michaelabed@gmail.com> | 2012-04-05 15:53:47 -0400 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-04-05 15:53:47 -0400 |
| commit | c5c3101483a4c2facd67f514f0c320b4192f5844 (patch) | |
| tree | c21262d3e8fadcb21d15da484997b56798f05307 | |
| download | ec311-lab6-master.tar.gz ec311-lab6-master.tar.bz2 ec311-lab6-master.zip | |
46 files changed, 2596 insertions, 0 deletions
diff --git a/ClockDivider.v b/ClockDivider.v new file mode 100644 index 0000000..7ced5a7 --- /dev/null +++ b/ClockDivider.v @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:24:11 03/16/2012 +// Design Name: +// Module Name: ClockDivider +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ClockDivider( + input clk_in, + input rst, + input [23:0] count, + output clk_out + ); + +reg clk_out = 0; +reg [23:0] c = 0; + +always @(posedge clk_in or posedge rst) begin + if (rst == 1) begin + c = 0; + clk_out = 0; + end else if (c == count) begin + clk_out = ~clk_out; + c = 0; + end else begin + c = c + 24'd1; + end + + +end + + + +endmodule diff --git a/Detector.v b/Detector.v new file mode 100644 index 0000000..f1bba2a --- /dev/null +++ b/Detector.v @@ -0,0 +1,66 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:38:26 04/05/2012 +// Design Name: +// Module Name: Detector +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Detector( + input inp, + input clk, + input rst, + output result, + output [1:0] state + ); + +reg [1:0] state; +reg [1:0] nextstate; +reg result; + +initial begin + state = 0; + result = 0; +end + +always @(posedge clk or posedge rst) begin + if (rst) begin + state <= 0; + end else begin + state <= nextstate; + end +end + +always @(*) begin + case (state) + 2'b00: nextstate = inp ? 2'b01 : 2'b00; + 2'b01: nextstate = inp ? 2'b10 : 2'b00; + 2'b10: nextstate = inp ? 2'b11 : 2'b00; + 2'b11: nextstate = inp ? 2'b11 : 2'b00; + default: nextstate = 2'b00; + endcase +end + +always @(state) begin + case (state) + 2'b00: result = 0; + 2'b01: result = 0; + 2'b10: result = 0; + 2'b11: result = 1; + default: result = 0; + endcase +end + +endmodule diff --git a/Detector_summary.html b/Detector_summary.html new file mode 100644 index 0000000..559c488 --- /dev/null +++ b/Detector_summary.html @@ -0,0 +1,79 @@ +<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD> +<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> +<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'> +<TD ALIGN=CENTER COLSPAN='4'><B>Detector Project Status</B></TD></TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> +<TD>lab6.xise</TD> +<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> +<TD> No Errors </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> +<TD>Detector</TD> +<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> +<TD>New</TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> +<TD>xc6slx16-3csg324</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> +<TD>Balanced</TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> +<TD> + </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> +<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD> +<TD> </TD> +</TR> +<TR ALIGN=LEFT> +<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> +<TD> </TD> +<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> +<TD> </TD> +</TR> +</TABLE> + + + + + + + + + + + + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> +<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> +<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> +<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> +</TABLE> + <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> +<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> +</TABLE> + + +<br><center><b>Date Generated:</b> 04/05/2012 - 15:00:11</center> +</BODY></HTML>
\ No newline at end of file diff --git a/DisplayController.v b/DisplayController.v new file mode 100644 index 0000000..9e4cc66 --- /dev/null +++ b/DisplayController.v @@ -0,0 +1,48 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:03:47 03/16/2012 +// Design Name: +// Module Name: DisplayController +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module DisplayController( + input [3:0] A, + input [3:0] B, + input clk_in, + input rst, + output [6:0] result, + output [3:0] AN + ); + +reg [3:0] AN; +reg [6:0] result = 0; + +wire [6:0] ssd1; +wire [6:0] ssd2; + +reg prev = 0; + +SevSegDisp d1(.A(A), .result(ssd1)); +SevSegDisp d2(.A(B), .result(ssd2)); + +always @( posedge clk_in ) begin + prev <= ~prev; + result <= prev ? ssd1 : ssd2; + AN <= { ~prev, 2'b11, prev }; +end + + +endmodule diff --git a/FSMController.v b/FSMController.v new file mode 100644 index 0000000..65cd70b --- /dev/null +++ b/FSMController.v @@ -0,0 +1,63 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:33:05 04/05/2012 +// Design Name: +// Module Name: FSMController +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module FSMController( + input clk, + input btn, + input [7:0] pattern, + input rst, + output [6:0] ssd, + output [3:0] an + ); +reg [6:0] ssd; +reg [3:0] an; + +reg [2:0] idx; + +wire inp; +wire dbbtn; +wire dbclk; +wire dpclk; +wire res; +wire [1:0] state; +wire [6:0] ssdw; +wire [3:0] anw; + +ClockDivider cdiv(.count(100), .rst(rst), .clk_in(clk), .clk_out(dbclk)); +ClockDivider dclk(.count(75000), .rst(rst), .clk_in(clk), .clk_out(dpclk)); +debouncer dbclk(.clk_1M(dbclk), .rst(rst), .din(btn), .dout(dbbtn)); + +Detector d(.inp(inp), .clk(dbbtn), .rst(rst), .result(res), .state(state)); + +DisplayController dc(.A({2'b00, state}), .B({3'b000, res}), .rst(rst), .clk_in(dpclk), .result(ssdw), .AN(anw)); + +initial begin + idx = 0; +end + +assign ssd = ssdw; +assign an = anw; + +always @(posedge clk) begin + idx = idx + 1; + inp <= inp[7-idx]; +end + +endmodule diff --git a/SevSegDisp.v b/SevSegDisp.v new file mode 100644 index 0000000..8d2c3b1 --- /dev/null +++ b/SevSegDisp.v @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:01:14 03/16/2012 +// Design Name: +// Module Name: SevSegDisp +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module SevSegDisp( + input [3:0] A, + output [6:0] result + ); + +reg [6:0] result = 0; + +always @ ( * ) begin + case ( A ) + 4'b0000 : result = 7'b0000001; + 4'b0001 : result = 7'b1001111; + 4'b0010 : result = 7'b0010010; + 4'b0011 : result = 7'b0000110; + 4'b0100 : result = 7'b1001100; + 4'b0101 : result = 7'b0100100; + 4'b0110 : result = 7'b0100000; + 4'b0111 : result = 7'b0001111; + 4'b1000 : result = 7'b0000000; + 4'b1001 : result = 7'b0001100; + default : result = 7'b0011010; + endcase +end + +endmodule diff --git a/TEST_Detector.v b/TEST_Detector.v new file mode 100644 index 0000000..8f038f8 --- /dev/null +++ b/TEST_Detector.v @@ -0,0 +1,66 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:01:00 04/05/2012 +// Design Name: Detector +// Module Name: /home/michael/Documents/School/EC311/lab6/TEST_Detector.v +// Project Name: lab6 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: Detector +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_Detector; + + // Inputs + reg inp; + reg clk; + reg rst; + + // Outputs + wire result; + wire [1:0] state; + + // Instantiate the Unit Under Test (UUT) + Detector uut ( + .inp(inp), + .clk(clk), + .rst(rst), + .result(result), + .state(state) + ); + + reg [19:0] pattern = 20'b11010111011111110110; + reg [15:0] i; + initial begin + // Initialize Inputs + inp = 0; + clk = 0; + rst = 0; + i = 0; + + // Wait 100 ns for global reset to finish + #50; + + // Add stimulus here + for (i = 0; i < 20; i = i + 1) begin + inp = pattern[19-i]; + clk = ~clk; #5; + clk = ~clk; #5; + end + end + +endmodule + diff --git a/TEST_Detector_beh.prj b/TEST_Detector_beh.prj new file mode 100644 index 0000000..725319e --- /dev/null +++ b/TEST_Detector_beh.prj @@ -0,0 +1,3 @@ +verilog work "Detector.v" +verilog work "TEST_Detector.v" +verilog work "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" diff --git a/TEST_Detector_isim_beh.exe b/TEST_Detector_isim_beh.exe Binary files differnew file mode 100755 index 0000000..beb9ccd --- /dev/null +++ b/TEST_Detector_isim_beh.exe diff --git a/TEST_Detector_isim_beh.wdb b/TEST_Detector_isim_beh.wdb Binary files differnew file mode 100644 index 0000000..093e2eb --- /dev/null +++ b/TEST_Detector_isim_beh.wdb diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..54b96d0 --- /dev/null +++ b/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated --> +<!-- by the Xilinx ISE software. Any direct editing or --> +<!-- changes made to this file may result in unpredictable --> +<!-- behavior or data corruption. It is strongly advised that --> +<!-- users do not edit the contents of this file. --> +<!-- --> +<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> + +<messages> +<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "/home/michael/Documents/School/EC311/lab6/FSMController.v" into library work</arg> +</msg> + +</messages> + diff --git a/debouncer.v b/debouncer.v new file mode 100644 index 0000000..d37cf6d --- /dev/null +++ b/debouncer.v @@ -0,0 +1,56 @@ +module debouncer(clk_1M, rst, din, dout);
+ input clk_1M;
+ input rst;
+ input din;
+ output dout;
+
+ reg dout;
+ reg [21:0] count;
+
+ reg sync0; // first stage of synchronizer
+ reg sync1; // second stage of synchronizer
+
+ reg prev; // register for edge detection
+
+ // synchronize input. (Synchronizers will be discussed in a future lab.)
+ always @(posedge clk_1M or posedge rst) begin
+ if (rst == 1) begin
+ sync0 <= 0;
+ sync1 <= 0;
+ end
+ else begin
+ sync0 <= din;
+ sync1 <= sync0;
+ end
+ end // always
+
+ // perform an edge detect on the synchronized input.
+ always @(posedge clk_1M or posedge rst) begin
+ if (rst == 1) begin
+ prev <= 0;
+ end
+ else begin
+ prev <= sync1;
+ end
+ end // always
+
+ // state machine/counter for timing the debouncing.
+ always @(posedge clk_1M or posedge rst) begin
+ if (rst == 1) begin
+ count <= 0;
+ end
+ else begin
+ if (count == 0) begin
+ if (sync1 == 1 && prev == 0) begin // rising edge detect
+ count <= 22'd100000; // 100,000 us = 100ms delay
+ end
+ dout <= 0;
+ end
+ else begin
+ count <= count - 22'd1;
+ dout <= 1;
+ end
+ end
+ end // always
+
+endmodule
diff --git a/detector.wcfg b/detector.wcfg new file mode 100644 index 0000000..1310b38 --- /dev/null +++ b/detector.wcfg @@ -0,0 +1,43 @@ +<?xml version="1.0" encoding="UTF-8"?> +<wave_config> + <wave_state> + </wave_state> + <db_ref_list> + <db_ref path="/home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.wdb" id="1" type="auto"> + <top_modules> + <top_module name="TEST_Detector" /> + <top_module name="glbl" /> + </top_modules> + </db_ref> + </db_ref_list> + <WVObjectSize size="7" /> + <wvobject fp_name="/TEST_Detector/result" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">result</obj_property> + <obj_property name="ObjectShortName">result</obj_property> + </wvobject> + <wvobject fp_name="/TEST_Detector/state" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">state[1:0]</obj_property> + <obj_property name="ObjectShortName">state[1:0]</obj_property> + </wvobject> + <wvobject fp_name="/TEST_Detector/inp" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">inp</obj_property> + <obj_property name="ObjectShortName">inp</obj_property> + </wvobject> + <wvobject fp_name="/TEST_Detector/clk" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">clk</obj_property> + <obj_property name="ObjectShortName">clk</obj_property> + </wvobject> + <wvobject fp_name="/TEST_Detector/rst" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">rst</obj_property> + <obj_property name="ObjectShortName">rst</obj_property> + </wvobject> + <wvobject fp_name="/TEST_Detector/pattern" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">pattern[15:0]</obj_property> + <obj_property name="ObjectShortName">pattern[15:0]</obj_property> + <obj_property name="Radix">BINARYRADIX</obj_property> + </wvobject> + <wvobject fp_name="/TEST_Detector/i" type="array" db_ref_id="1"> + <obj_property name="ElementShortName">i[15:0]</obj_property> + <obj_property name="ObjectShortName">i[15:0]</obj_property> + </wvobject> +</wave_config> diff --git a/fuse.log b/fuse.log new file mode 100644 index 0000000..44e0298 --- /dev/null +++ b/fuse.log @@ -0,0 +1,24 @@ +Running: /home/michael/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "/home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.exe" -prj "/home/michael/Documents/School/EC311/lab6/TEST_Detector_beh.prj" "work.TEST_Detector" "work.glbl" +ISim O.87xd (signature 0x8ddf5b5d) +Number of CPUs detected in this system: 2 +Turning on mult-threading, number of parallel sub-compilation jobs: 4 +Determining compilation order of HDL files +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab6/Detector.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab6/Detector.v" Line 29: Redeclaration of ansi port state is not allowed +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab6/Detector.v" Line 31: Redeclaration of ansi port result is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab6/TEST_Detector.v" into library work +Analyzing Verilog file "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" into library work +Starting static elaboration +Completed static elaboration +Fuse Memory Usage: 94996 KB +Fuse CPU Usage: 1550 ms +Compiling module Detector +Compiling module TEST_Detector +Compiling module glbl +Time Resolution for simulation is 1ps. +Waiting for 1 sub-compilation(s) to finish... +Compiled 3 Verilog Units +Built simulation executable /home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.exe +Fuse Memory Usage: 393016 KB +Fuse CPU Usage: 1580 ms +GCC CPU Usage: 380 ms diff --git a/fuse.xmsgs b/fuse.xmsgs new file mode 100644 index 0000000..cc5dbd1 --- /dev/null +++ b/fuse.xmsgs @@ -0,0 +1,15 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated + by the Xilinx ISE software. Any direct editing or + changes made to this file may result in unpredictable + behavior or data corruption. It is strongly advised that + users do not edit the contents of this file. --> +<messages> +<msg type="warning" file="HDLCompiler" num="751" delta="unknown" >"/home/michael/Documents/School/EC311/lab6/Detector.v" Line 29: Redeclaration of ansi port <arg fmt="%s" index="1">state</arg> is not allowed +</msg> + +<msg type="warning" file="HDLCompiler" num="751" delta="unknown" >"/home/michael/Documents/School/EC311/lab6/Detector.v" Line 31: Redeclaration of ansi port <arg fmt="%s" index="1">result</arg> is not allowed +</msg> + +</messages> + diff --git a/fuseRelaunch.cmd b/fuseRelaunch.cmd new file mode 100644 index 0000000..f303178 --- /dev/null +++ b/fuseRelaunch.cmd @@ -0,0 +1 @@ +-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "/home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.exe" -prj "/home/michael/Documents/School/EC311/lab6/TEST_Detector_beh.prj" "work.TEST_Detector" "work.glbl" diff --git a/iseconfig/Detector.xreport b/iseconfig/Detector.xreport new file mode 100644 index 0000000..2f9d918 --- /dev/null +++ b/iseconfig/Detector.xreport @@ -0,0 +1,215 @@ +<?xml version='1.0' encoding='UTF-8'?> +<report-views version="2.0" > + <header> + <DateModified>2012-04-05T15:00:11</DateModified> + <ModuleName>Detector</ModuleName> + <SummaryTimeStamp>Unknown</SummaryTimeStamp> + <SavedFilePath>/home/michael/Documents/School/EC311/lab6/iseconfig/Detector.xreport</SavedFilePath> + <ImplementationReportsDirectory>/home/michael/Documents/School/EC311/lab6</ImplementationReportsDirectory> + <DateInitialized>2012-04-05T15:00:10</DateInitialized> + <EnableMessageFiltering>false</EnableMessageFiltering> + </header> + <body> + <viewgroup label="Design Overview" > + <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="Detector_summary.html" label="Summary" > + <toc-item title="Design Overview" target="Design Overview" /> + <toc-item title="Design Utilization Summary" target="Design Utilization Summary" /> + <toc-item title="Performance Summary" target="Performance Summary" /> + <toc-item title="Failing Constraints" target="Failing Constraints" /> + <toc-item title="Detailed Reports" target="Detailed Reports" /> + </view> + <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="Detector_envsettings.html" label="System Settings" /> + <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="Detector_map.xrpt" label="IOB Properties" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="Detector_map.xrpt" label="Control Set Information" /> + <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="Detector_map.xrpt" label="Module Level Utilization" /> + <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="Detector.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" /> + <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="Detector_par.xrpt" label="Pinout Report" /> + <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="Detector_par.xrpt" label="Clock Report" /> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="Detector.twx" label="Static Timing" /> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="Detector_html/fit/report.htm" label="CPLD Fitter Report" /> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="Detector_html/tim/report.htm" label="CPLD Timing Report" /> + </viewgroup> + <viewgroup label="XPS Errors and Warnings" > + <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" /> + <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" /> + <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" /> + </viewgroup> + <viewgroup label="XPS Reports" > + <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" /> + <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" /> + <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" /> + <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="Detector.log" label="System Log File" /> + </viewgroup> + <viewgroup label="Errors and Warnings" > + <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" /> + <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" /> + <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" /> + <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" /> + <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" /> + <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" /> + <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" /> + <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" /> + <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" /> + <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" /> + <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" /> + </viewgroup> + <viewgroup label="Detailed Reports" > + <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="Detector.syr" label="Synthesis Report" > + <toc-item title="Top of Report" target="Copyright " searchDir="Forward" /> + <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " /> + <toc-item title="HDL Compilation" target=" HDL Compilation " /> + <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " /> + <toc-item title="HDL Analysis" target=" HDL Analysis " /> + <toc-item title="HDL Parsing" target=" HDL Parsing " /> + <toc-item title="HDL Elaboration" target=" HDL Elaboration " /> + <toc-item title="HDL Synthesis" target=" HDL Synthesis " /> + <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" /> + <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" /> + <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" /> + <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " /> + <toc-item title="Partition Report" target=" Partition Report " /> + <toc-item title="Final Report" target=" Final Report " /> + <toc-item title="Design Summary" target=" Design Summary " /> + <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" /> + <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" /> + <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" /> + <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" /> + <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" /> + <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" /> + <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" /> + <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" /> + <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" /> + </view> + <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="Detector.srr" label="Synplify Report" /> + <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="Detector.prec_log" label="Precision Report" /> + <view inputState="Synthesized" program="ngdbuild" type="Report" file="Detector.bld" label="Translation Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Command Line" target="Command Line:" /> + <toc-item title="Partition Status" target="Partition Implementation Status" /> + <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" /> + </view> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="Detector_map.mrp" label="Map Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" /> + <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" /> + <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" /> + <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" /> + <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" /> + <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" /> + <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" /> + <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" /> + <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" /> + <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" /> + <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" /> + <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" /> + <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="Detector.par" label="Place and Route Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Device Utilization" target="Device Utilization Summary:" /> + <toc-item title="Router Information" target="Starting Router" /> + <toc-item title="Partition Status" target="Partition Implementation Status" /> + <toc-item title="Clock Report" target="Generating Clock Report" /> + <toc-item title="Timing Results" target="Timing Score:" /> + <toc-item title="Final Summary" target="Peak Memory Usage:" /> + </view> + <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="Detector.twr" label="Post-PAR Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item title="Warning Messages" target="WARNING:" /> + <toc-item title="Timing Constraints" target="Timing constraint:" /> + <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="Detector.rpt" label="CPLD Fitter Report (Text)" > + <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" /> + <toc-item title="Resources Summary" target="** Mapped Resource Summary **" /> + <toc-item title="Pin Resources" target="** Pin Resources **" /> + <toc-item title="Global Resources" target="** Global Control Resources **" /> + </view> + <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="Detector.tim" label="CPLD Timing Report (Text)" > + <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" /> + <toc-item title="Performance Summary" target="Performance Summary:" /> + </view> + <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="Detector.pwr" label="Power Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Power summary" target="Power summary" /> + <toc-item title="Thermal summary" target="Thermal summary" /> + </view> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="Detector.bgn" label="Bitgen Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" /> + <toc-item title="Final Summary" target="DRC detected" /> + </view> + </viewgroup> + <viewgroup label="Secondary Reports" > + <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" /> + <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/Detector_synthesis.nlf" label="Post-Synthesis Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/Detector_translate.nlf" label="Post-Translate Simulation Model Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="Detector_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" /> + <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="Detector_map.map" label="Map Log File" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + <toc-item title="Design Information" target="Design Information" /> + <toc-item title="Design Summary" target="Design Summary" /> + </view> + <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" /> + <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Detector_preroute.twr" label="Post-Map Static Timing Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + <toc-item title="Timing Report Description" target="Device,package,speed:" /> + <toc-item title="Informational Messages" target="INFO:" /> + <toc-item title="Warning Messages" target="WARNING:" /> + <toc-item title="Timing Constraints" target="Timing constraint:" /> + <toc-item title="Derived Constraint Report" target="Derived Constraint Report" /> + <toc-item title="Data Sheet Report" target="Data Sheet report:" /> + <toc-item title="Timing Summary" target="Timing summary:" /> + <toc-item title="Trace Settings" target="Trace Settings:" /> + </view> + <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/Detector_map.nlf" label="Post-Map Simulation Model Report" /> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Detector_map.psr" label="Physical Synthesis Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="Detector_pad.txt" label="Pad Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="Detector.unroutes" label="Unroutes Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Detector_preroute.tsi" label="Post-Map Constraints Interaction Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Detector.grf" label="Guide Results Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Detector.dly" label="Asynchronous Delay Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Detector.clk_rgn" label="Clock Region Report" /> + <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Detector.tsi" label="Post-Place and Route Constraints Interaction Report" > + <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" /> + </view> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="Detector_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" /> + <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/Detector_timesim.nlf" label="Post-Place and Route Simulation Model Report" /> + <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="Detector_sta.nlf" label="Primetime Netlist Report" > + <toc-item title="Top of Report" target="Release" searchDir="Forward" /> + </view> + <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="Detector.ibs" label="IBIS Model" > + <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" /> + <toc-item title="Component" target="Component " /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Detector.lck" label="Back-annotate Pin Report" > + <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" /> + <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" /> + </view> + <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Detector.lpc" label="Locked Pin Constraints" > + <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" /> + <toc-item title="Newly Added Constraints" target="The following constraints were newly added" /> + </view> + <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/Detector_timesim.nlf" label="Post-Fit Simulation Model Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" /> + <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" /> + </viewgroup> + </body> +</report-views> diff --git a/iseconfig/lab6.projectmgr b/iseconfig/lab6.projectmgr new file mode 100644 index 0000000..d839514 --- /dev/null +++ b/iseconfig/lab6.projectmgr @@ -0,0 +1,58 @@ +<?xml version="1.0" encoding="utf-8"?> +<!--This is an ISE project configuration file.--> +<!--It holds project specific layout data for the projectmgr plugin.--> +<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.--> +<Project version="2" owner="projectmgr" name="lab6" > + <!--This is an ISE project configuration file.--> + <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" > + <ClosedNodes> + <ClosedNodesVersion>2</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems> + <SelectedItem>Unassigned User Library Modules</SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000144000000020000000100000000000000000200000064ffffffff000000810000000300000002000001440000000100000003000000000000000100000003</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> + <CurrentItem>Unassigned User Library Modules</CurrentItem> + </ItemView> + <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + <ClosedNode>Design Utilities</ClosedNode> + </ClosedNodes> + <SelectedItems> + <SelectedItem></SelectedItem> + </SelectedItems> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000154000000010000000100000000000000000000000064ffffffff000000810000000000000001000001540000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem></CurrentItem> + </ItemView> + <ItemView guiview="File" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems/> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000157000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004a00000001000000000000002800000001000000000000007900000001000000000000006c0000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem></CurrentItem> + </ItemView> + <ItemView guiview="Library" > + <ClosedNodes> + <ClosedNodesVersion>1</ClosedNodesVersion> + </ClosedNodes> + <SelectedItems/> + <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> + <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> + <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000117000000010001000100000000000000000000000064ffffffff000000810000000000000001000001170000000100000000</ViewHeaderState> + <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> + <CurrentItem>work</CurrentItem> + </ItemView> + <SourceProcessView>000000ff00000000000000020000013f0000012001000000060100000002</SourceProcessView> + <CurrentView>Implementation</CurrentView> +</Project> diff --git a/isim.cmd b/isim.cmd new file mode 100644 index 0000000..fff18e8 --- /dev/null +++ b/isim.cmd @@ -0,0 +1,3 @@ +onerror {resume} +wave add / +run 1000 ns; diff --git a/isim.log b/isim.log new file mode 100644 index 0000000..4490dcf --- /dev/null +++ b/isim.log @@ -0,0 +1,37 @@ +ISim log file +Running: /home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.wdb +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +Time resolution is 1 ps +# onerror resume +# wave add / +# run 1000 ns +Simulator is doing circuit initialization process. +Finished circuit initialization process. +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +Finished circuit initialization process. +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +Finished circuit initialization process. +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +Finished circuit initialization process. diff --git a/isim/TEST_Detector_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg b/isim/TEST_Detector_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg Binary files differnew file mode 100644 index 0000000..c92f755 --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg diff --git a/isim/TEST_Detector_isim_beh.exe.sim/TEST_Detector_isim_beh.exe b/isim/TEST_Detector_isim_beh.exe.sim/TEST_Detector_isim_beh.exe Binary files differnew file mode 100755 index 0000000..d1311cc --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/TEST_Detector_isim_beh.exe diff --git a/isim/TEST_Detector_isim_beh.exe.sim/isimcrash.log b/isim/TEST_Detector_isim_beh.exe.sim/isimcrash.log new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/isimcrash.log diff --git a/isim/TEST_Detector_isim_beh.exe.sim/isimkernel.log b/isim/TEST_Detector_isim_beh.exe.sim/isimkernel.log new file mode 100644 index 0000000..52d56ea --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/isimkernel.log @@ -0,0 +1,10 @@ +Command line: + TEST_Detector_isim_beh.exe + -simmode gui + -simrunnum 0 + -socket 42292 + +Thu Apr 5 15:29:09 2012 + + + Elaboration Time: 0.01 sec diff --git a/isim/TEST_Detector_isim_beh.exe.sim/netId.dat b/isim/TEST_Detector_isim_beh.exe.sim/netId.dat Binary files differnew file mode 100644 index 0000000..6f94b14 --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/netId.dat diff --git a/isim/TEST_Detector_isim_beh.exe.sim/tmp_save/_1 b/isim/TEST_Detector_isim_beh.exe.sim/tmp_save/_1 Binary files differnew file mode 100644 index 0000000..ce05ccc --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/tmp_save/_1 diff --git a/isim/TEST_Detector_isim_beh.exe.sim/work/TEST_Detector_isim_beh.exe_main.c b/isim/TEST_Detector_isim_beh.exe.sim/work/TEST_Detector_isim_beh.exe_main.c new file mode 100644 index 0000000..8e9fb43 --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/work/TEST_Detector_isim_beh.exe_main.c @@ -0,0 +1,36 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +#include "xsi.h" + +struct XSI_INFO xsi_info; + + + +int main(int argc, char **argv) +{ + xsi_init_design(argc, argv); + xsi_register_info(&xsi_info); + + xsi_register_min_prec_unit(-12); + work_m_13872111861810629931_1087962131_init(); + work_m_14253225476704866645_1235880303_init(); + work_m_16541823861846354283_2073120511_init(); + + + xsi_register_tops("work_m_14253225476704866645_1235880303"); + xsi_register_tops("work_m_16541823861846354283_2073120511"); + + + return xsi_run_simulation(argc, argv); + +} diff --git a/isim/TEST_Detector_isim_beh.exe.sim/work/TEST_Detector_isim_beh.exe_main.lin64.o b/isim/TEST_Detector_isim_beh.exe.sim/work/TEST_Detector_isim_beh.exe_main.lin64.o Binary files differnew file mode 100644 index 0000000..7e43768 --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/work/TEST_Detector_isim_beh.exe_main.lin64.o diff --git a/isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.c b/isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.c new file mode 100644 index 0000000..47cffce --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.c @@ -0,0 +1,547 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab6/Detector.v"; +static int ng1[] = {0, 0}; +static unsigned int ng2[] = {0U, 0U}; +static unsigned int ng3[] = {1U, 0U}; +static unsigned int ng4[] = {2U, 0U}; +static unsigned int ng5[] = {3U, 0U}; +static int ng6[] = {1, 0}; + + + +static void Initial_33_0(char *t0) +{ + char *t1; + char *t2; + +LAB0: xsi_set_current_line(33, ng0); + +LAB2: xsi_set_current_line(34, ng0); + t1 = ((char*)((ng1))); + t2 = (t0 + 1928); + xsi_vlogvar_assign_value(t2, t1, 0, 0, 2); + xsi_set_current_line(35, ng0); + t1 = ((char*)((ng1))); + t2 = (t0 + 1768); + xsi_vlogvar_assign_value(t2, t1, 0, 0, 1); + +LAB1: return; +} + +static void Always_38_1(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + unsigned int t6; + unsigned int t7; + unsigned int t8; + unsigned int t9; + unsigned int t10; + char *t11; + char *t12; + +LAB0: t1 = (t0 + 3248U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(38, ng0); + t2 = (t0 + 4064); + *((int *)t2) = 1; + t3 = (t0 + 3280); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(38, ng0); + +LAB5: xsi_set_current_line(39, ng0); + t4 = (t0 + 1368U); + t5 = *((char **)t4); + t4 = (t5 + 4); + t6 = *((unsigned int *)t4); + t7 = (~(t6)); + t8 = *((unsigned int *)t5); + t9 = (t8 & t7); + t10 = (t9 != 0); + if (t10 > 0) + goto LAB6; + +LAB7: xsi_set_current_line(41, ng0); + +LAB10: xsi_set_current_line(42, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 1928); + xsi_vlogvar_wait_assign_value(t5, t4, 0, 0, 2, 0LL); + +LAB8: goto LAB2; + +LAB6: xsi_set_current_line(39, ng0); + +LAB9: xsi_set_current_line(40, ng0); + t11 = ((char*)((ng1))); + t12 = (t0 + 1928); + xsi_vlogvar_wait_assign_value(t12, t11, 0, 0, 2, 0LL); + goto LAB8; + +} + +static void Always_46_2(char *t0) +{ + char t9[8]; + char t10[8]; + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + int t8; + char *t11; + char *t12; + unsigned int t13; + unsigned int t14; + unsigned int t15; + unsigned int t16; + unsigned int t17; + char *t18; + char *t19; + unsigned int t20; + unsigned int t21; + unsigned int t22; + char *t23; + unsigned int t24; + unsigned int t25; + unsigned int t26; + unsigned int t27; + char *t28; + char *t29; + +LAB0: t1 = (t0 + 3496U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(46, ng0); + t2 = (t0 + 4080); + *((int *)t2) = 1; + t3 = (t0 + 3528); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(46, ng0); + +LAB5: xsi_set_current_line(47, ng0); + t4 = (t0 + 1928); + t5 = (t4 + 56U); + t6 = *((char **)t5); + +LAB6: t7 = ((char*)((ng2))); + t8 = xsi_vlog_unsigned_case_compare(t6, 2, t7, 2); + if (t8 == 1) + goto LAB7; + +LAB8: t2 = ((char*)((ng3))); + t8 = xsi_vlog_unsigned_case_compare(t6, 2, t2, 2); + if (t8 == 1) + goto LAB9; + +LAB10: t2 = ((char*)((ng4))); + t8 = xsi_vlog_unsigned_case_compare(t6, 2, t2, 2); + if (t8 == 1) + goto LAB11; + +LAB12: t2 = ((char*)((ng5))); + t8 = xsi_vlog_unsigned_case_compare(t6, 2, t2, 2); + if (t8 == 1) + goto LAB13; + +LAB14: +LAB16: +LAB15: xsi_set_current_line(52, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 2088); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 2); + +LAB17: goto LAB2; + +LAB7: xsi_set_current_line(48, ng0); + t11 = (t0 + 1048U); + t12 = *((char **)t11); + memset(t10, 0, 8); + t11 = (t12 + 4); + t13 = *((unsigned int *)t11); + t14 = (~(t13)); + t15 = *((unsigned int *)t12); + t16 = (t15 & t14); + t17 = (t16 & 1U); + if (t17 != 0) + goto LAB18; + +LAB19: if (*((unsigned int *)t11) != 0) + goto LAB20; + +LAB21: t19 = (t10 + 4); + t20 = *((unsigned int *)t10); + t21 = *((unsigned int *)t19); + t22 = (t20 || t21); + if (t22 > 0) + goto LAB22; + +LAB23: t24 = *((unsigned int *)t10); + t25 = (~(t24)); + t26 = *((unsigned int *)t19); + t27 = (t25 || t26); + if (t27 > 0) + goto LAB24; + +LAB25: if (*((unsigned int *)t19) > 0) + goto LAB26; + +LAB27: if (*((unsigned int *)t10) > 0) + goto LAB28; + +LAB29: memcpy(t9, t28, 8); + +LAB30: t29 = (t0 + 2088); + xsi_vlogvar_assign_value(t29, t9, 0, 0, 2); + goto LAB17; + +LAB9: xsi_set_current_line(49, ng0); + t3 = (t0 + 1048U); + t4 = *((char **)t3); + memset(t10, 0, 8); + t3 = (t4 + 4); + t13 = *((unsigned int *)t3); + t14 = (~(t13)); + t15 = *((unsigned int *)t4); + t16 = (t15 & t14); + t17 = (t16 & 1U); + if (t17 != 0) + goto LAB31; + +LAB32: if (*((unsigned int *)t3) != 0) + goto LAB33; + +LAB34: t7 = (t10 + 4); + t20 = *((unsigned int *)t10); + t21 = *((unsigned int *)t7); + t22 = (t20 || t21); + if (t22 > 0) + goto LAB35; + +LAB36: t24 = *((unsigned int *)t10); + t25 = (~(t24)); + t26 = *((unsigned int *)t7); + t27 = (t25 || t26); + if (t27 > 0) + goto LAB37; + +LAB38: if (*((unsigned int *)t7) > 0) + goto LAB39; + +LAB40: if (*((unsigned int *)t10) > 0) + goto LAB41; + +LAB42: memcpy(t9, t12, 8); + +LAB43: t18 = (t0 + 2088); + xsi_vlogvar_assign_value(t18, t9, 0, 0, 2); + goto LAB17; + +LAB11: xsi_set_current_line(50, ng0); + t3 = (t0 + 1048U); + t4 = *((char **)t3); + memset(t10, 0, 8); + t3 = (t4 + 4); + t13 = *((unsigned int *)t3); + t14 = (~(t13)); + t15 = *((unsigned int *)t4); + t16 = (t15 & t14); + t17 = (t16 & 1U); + if (t17 != 0) + goto LAB44; + +LAB45: if (*((unsigned int *)t3) != 0) + goto LAB46; + +LAB47: t7 = (t10 + 4); + t20 = *((unsigned int *)t10); + t21 = *((unsigned int *)t7); + t22 = (t20 || t21); + if (t22 > 0) + goto LAB48; + +LAB49: t24 = *((unsigned int *)t10); + t25 = (~(t24)); + t26 = *((unsigned int *)t7); + t27 = (t25 || t26); + if (t27 > 0) + goto LAB50; + +LAB51: if (*((unsigned int *)t7) > 0) + goto LAB52; + +LAB53: if (*((unsigned int *)t10) > 0) + goto LAB54; + +LAB55: memcpy(t9, t12, 8); + +LAB56: t18 = (t0 + 2088); + xsi_vlogvar_assign_value(t18, t9, 0, 0, 2); + goto LAB17; + +LAB13: xsi_set_current_line(51, ng0); + t3 = (t0 + 1048U); + t4 = *((char **)t3); + memset(t10, 0, 8); + t3 = (t4 + 4); + t13 = *((unsigned int *)t3); + t14 = (~(t13)); + t15 = *((unsigned int *)t4); + t16 = (t15 & t14); + t17 = (t16 & 1U); + if (t17 != 0) + goto LAB57; + +LAB58: if (*((unsigned int *)t3) != 0) + goto LAB59; + +LAB60: t7 = (t10 + 4); + t20 = *((unsigned int *)t10); + t21 = *((unsigned int *)t7); + t22 = (t20 || t21); + if (t22 > 0) + goto LAB61; + +LAB62: t24 = *((unsigned int *)t10); + t25 = (~(t24)); + t26 = *((unsigned int *)t7); + t27 = (t25 || t26); + if (t27 > 0) + goto LAB63; + +LAB64: if (*((unsigned int *)t7) > 0) + goto LAB65; + +LAB66: if (*((unsigned int *)t10) > 0) + goto LAB67; + +LAB68: memcpy(t9, t12, 8); + +LAB69: t18 = (t0 + 2088); + xsi_vlogvar_assign_value(t18, t9, 0, 0, 2); + goto LAB17; + +LAB18: *((unsigned int *)t10) = 1; + goto LAB21; + +LAB20: t18 = (t10 + 4); + *((unsigned int *)t10) = 1; + *((unsigned int *)t18) = 1; + goto LAB21; + +LAB22: t23 = ((char*)((ng3))); + goto LAB23; + +LAB24: t28 = ((char*)((ng2))); + goto LAB25; + +LAB26: xsi_vlog_unsigned_bit_combine(t9, 2, t23, 2, t28, 2); + goto LAB30; + +LAB28: memcpy(t9, t23, 8); + goto LAB30; + +LAB31: *((unsigned int *)t10) = 1; + goto LAB34; + +LAB33: t5 = (t10 + 4); + *((unsigned int *)t10) = 1; + *((unsigned int *)t5) = 1; + goto LAB34; + +LAB35: t11 = ((char*)((ng4))); + goto LAB36; + +LAB37: t12 = ((char*)((ng2))); + goto LAB38; + +LAB39: xsi_vlog_unsigned_bit_combine(t9, 2, t11, 2, t12, 2); + goto LAB43; + +LAB41: memcpy(t9, t11, 8); + goto LAB43; + +LAB44: *((unsigned int *)t10) = 1; + goto LAB47; + +LAB46: t5 = (t10 + 4); + *((unsigned int *)t10) = 1; + *((unsigned int *)t5) = 1; + goto LAB47; + +LAB48: t11 = ((char*)((ng5))); + goto LAB49; + +LAB50: t12 = ((char*)((ng2))); + goto LAB51; + +LAB52: xsi_vlog_unsigned_bit_combine(t9, 2, t11, 2, t12, 2); + goto LAB56; + +LAB54: memcpy(t9, t11, 8); + goto LAB56; + +LAB57: *((unsigned int *)t10) = 1; + goto LAB60; + +LAB59: t5 = (t10 + 4); + *((unsigned int *)t10) = 1; + *((unsigned int *)t5) = 1; + goto LAB60; + +LAB61: t11 = ((char*)((ng5))); + goto LAB62; + +LAB63: t12 = ((char*)((ng2))); + goto LAB64; + +LAB65: xsi_vlog_unsigned_bit_combine(t9, 2, t11, 2, t12, 2); + goto LAB69; + +LAB67: memcpy(t9, t11, 8); + goto LAB69; + +} + +static void Always_56_3(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + int t8; + char *t9; + char *t10; + +LAB0: t1 = (t0 + 3744U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(56, ng0); + t2 = (t0 + 4096); + *((int *)t2) = 1; + t3 = (t0 + 3776); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(56, ng0); + +LAB5: xsi_set_current_line(57, ng0); + t4 = (t0 + 1928); + t5 = (t4 + 56U); + t6 = *((char **)t5); + +LAB6: t7 = ((char*)((ng2))); + t8 = xsi_vlog_unsigned_case_compare(t6, 2, t7, 2); + if (t8 == 1) + goto LAB7; + +LAB8: t2 = ((char*)((ng3))); + t8 = xsi_vlog_unsigned_case_compare(t6, 2, t2, 2); + if (t8 == 1) + goto LAB9; + +LAB10: t2 = ((char*)((ng4))); + t8 = xsi_vlog_unsigned_case_compare(t6, 2, t2, 2); + if (t8 == 1) + goto LAB11; + +LAB12: t2 = ((char*)((ng5))); + t8 = xsi_vlog_unsigned_case_compare(t6, 2, t2, 2); + if (t8 == 1) + goto LAB13; + +LAB14: +LAB16: +LAB15: xsi_set_current_line(62, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1768); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + +LAB17: goto LAB2; + +LAB7: xsi_set_current_line(58, ng0); + t9 = ((char*)((ng1))); + t10 = (t0 + 1768); + xsi_vlogvar_assign_value(t10, t9, 0, 0, 1); + goto LAB17; + +LAB9: xsi_set_current_line(59, ng0); + t3 = ((char*)((ng1))); + t4 = (t0 + 1768); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + goto LAB17; + +LAB11: xsi_set_current_line(60, ng0); + t3 = ((char*)((ng1))); + t4 = (t0 + 1768); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + goto LAB17; + +LAB13: xsi_set_current_line(61, ng0); + t3 = ((char*)((ng6))); + t4 = (t0 + 1768); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + goto LAB17; + +} + + +extern void work_m_13872111861810629931_1087962131_init() +{ + static char *pe[] = {(void *)Initial_33_0,(void *)Always_38_1,(void *)Always_46_2,(void *)Always_56_3}; + xsi_register_didat("work_m_13872111861810629931_1087962131", "isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.didat b/isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.didat Binary files differnew file mode 100644 index 0000000..6c3c7ba --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.didat diff --git a/isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.lin64.o b/isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.lin64.o Binary files differnew file mode 100644 index 0000000..45510b7 --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.lin64.o diff --git a/isim/TEST_Detector_isim_beh.exe.sim/work/m_14253225476704866645_1235880303.c b/isim/TEST_Detector_isim_beh.exe.sim/work/m_14253225476704866645_1235880303.c new file mode 100644 index 0000000..bab52a4 --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/work/m_14253225476704866645_1235880303.c @@ -0,0 +1,286 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab6/TEST_Detector.v"; +static int ng1[] = {0, 0}; +static int ng2[] = {20, 0}; +static int ng3[] = {19, 0}; +static int ng4[] = {1, 0}; + + + +static void Initial_47_0(char *t0) +{ + char t6[8]; + char t19[8]; + char t27[8]; + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t7; + char *t8; + char *t9; + char *t10; + unsigned int t11; + unsigned int t12; + unsigned int t13; + unsigned int t14; + unsigned int t15; + char *t16; + char *t17; + char *t18; + char *t20; + char *t21; + char *t22; + char *t23; + char *t24; + char *t25; + char *t26; + char *t28; + unsigned int t29; + unsigned int t30; + unsigned int t31; + unsigned int t32; + unsigned int t33; + unsigned int t34; + unsigned int t35; + unsigned int t36; + +LAB0: t1 = (t0 + 3160U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(47, ng0); + +LAB4: xsi_set_current_line(49, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1608); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(50, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1768); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(51, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 1928); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(52, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 2248); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 16); + xsi_set_current_line(55, ng0); + t2 = (t0 + 2968); + xsi_process_wait(t2, 50000LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(58, ng0); + xsi_set_current_line(58, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 2248); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 16); + +LAB6: t2 = (t0 + 2248); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = ((char*)((ng2))); + memset(t6, 0, 8); + t7 = (t4 + 4); + if (*((unsigned int *)t7) != 0) + goto LAB8; + +LAB7: t8 = (t5 + 4); + if (*((unsigned int *)t8) != 0) + goto LAB8; + +LAB11: if (*((unsigned int *)t4) < *((unsigned int *)t5)) + goto LAB9; + +LAB10: t10 = (t6 + 4); + t11 = *((unsigned int *)t10); + t12 = (~(t11)); + t13 = *((unsigned int *)t6); + t14 = (t13 & t12); + t15 = (t14 != 0); + if (t15 > 0) + goto LAB12; + +LAB13: goto LAB1; + +LAB8: t9 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t9) = 1; + goto LAB10; + +LAB9: *((unsigned int *)t6) = 1; + goto LAB10; + +LAB12: xsi_set_current_line(58, ng0); + +LAB14: xsi_set_current_line(59, ng0); + t16 = (t0 + 2088); + t17 = (t16 + 56U); + t18 = *((char **)t17); + t20 = (t0 + 2088); + t21 = (t20 + 72U); + t22 = *((char **)t21); + t23 = ((char*)((ng3))); + t24 = (t0 + 2248); + t25 = (t24 + 56U); + t26 = *((char **)t25); + memset(t27, 0, 8); + xsi_vlog_unsigned_minus(t27, 32, t23, 32, t26, 16); + xsi_vlog_generic_get_index_select_value(t19, 1, t18, t22, 2, t27, 32, 2); + t28 = (t0 + 1608); + xsi_vlogvar_assign_value(t28, t19, 0, 0, 1); + xsi_set_current_line(60, ng0); + t2 = (t0 + 1768); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t4 + 4); + t11 = *((unsigned int *)t5); + t12 = (~(t11)); + t13 = *((unsigned int *)t4); + t14 = (t13 & t12); + t15 = (t14 & 1U); + if (t15 != 0) + goto LAB18; + +LAB16: if (*((unsigned int *)t5) == 0) + goto LAB15; + +LAB17: t7 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t7) = 1; + +LAB18: t8 = (t6 + 4); + t9 = (t4 + 4); + t29 = *((unsigned int *)t4); + t30 = (~(t29)); + *((unsigned int *)t6) = t30; + *((unsigned int *)t8) = 0; + if (*((unsigned int *)t9) != 0) + goto LAB20; + +LAB19: t35 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t35 & 1U); + t36 = *((unsigned int *)t8); + *((unsigned int *)t8) = (t36 & 1U); + t10 = (t0 + 1768); + xsi_vlogvar_assign_value(t10, t6, 0, 0, 1); + xsi_set_current_line(60, ng0); + t2 = (t0 + 2968); + xsi_process_wait(t2, 5000LL); + *((char **)t1) = &&LAB21; + goto LAB1; + +LAB15: *((unsigned int *)t6) = 1; + goto LAB18; + +LAB20: t31 = *((unsigned int *)t6); + t32 = *((unsigned int *)t9); + *((unsigned int *)t6) = (t31 | t32); + t33 = *((unsigned int *)t8); + t34 = *((unsigned int *)t9); + *((unsigned int *)t8) = (t33 | t34); + goto LAB19; + +LAB21: xsi_set_current_line(61, ng0); + t2 = (t0 + 1768); + t3 = (t2 + 56U); + t4 = *((char **)t3); + memset(t6, 0, 8); + t5 = (t4 + 4); + t11 = *((unsigned int *)t5); + t12 = (~(t11)); + t13 = *((unsigned int *)t4); + t14 = (t13 & t12); + t15 = (t14 & 1U); + if (t15 != 0) + goto LAB25; + +LAB23: if (*((unsigned int *)t5) == 0) + goto LAB22; + +LAB24: t7 = (t6 + 4); + *((unsigned int *)t6) = 1; + *((unsigned int *)t7) = 1; + +LAB25: t8 = (t6 + 4); + t9 = (t4 + 4); + t29 = *((unsigned int *)t4); + t30 = (~(t29)); + *((unsigned int *)t6) = t30; + *((unsigned int *)t8) = 0; + if (*((unsigned int *)t9) != 0) + goto LAB27; + +LAB26: t35 = *((unsigned int *)t6); + *((unsigned int *)t6) = (t35 & 1U); + t36 = *((unsigned int *)t8); + *((unsigned int *)t8) = (t36 & 1U); + t10 = (t0 + 1768); + xsi_vlogvar_assign_value(t10, t6, 0, 0, 1); + xsi_set_current_line(61, ng0); + t2 = (t0 + 2968); + xsi_process_wait(t2, 5000LL); + *((char **)t1) = &&LAB28; + goto LAB1; + +LAB22: *((unsigned int *)t6) = 1; + goto LAB25; + +LAB27: t31 = *((unsigned int *)t6); + t32 = *((unsigned int *)t9); + *((unsigned int *)t6) = (t31 | t32); + t33 = *((unsigned int *)t8); + t34 = *((unsigned int *)t9); + *((unsigned int *)t8) = (t33 | t34); + goto LAB26; + +LAB28: xsi_set_current_line(58, ng0); + t2 = (t0 + 2248); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = ((char*)((ng4))); + memset(t6, 0, 8); + xsi_vlog_unsigned_add(t6, 32, t4, 16, t5, 32); + t7 = (t0 + 2248); + xsi_vlogvar_assign_value(t7, t6, 0, 0, 16); + goto LAB6; + +} + + +extern void work_m_14253225476704866645_1235880303_init() +{ + static char *pe[] = {(void *)Initial_47_0}; + xsi_register_didat("work_m_14253225476704866645_1235880303", "isim/TEST_Detector_isim_beh.exe.sim/work/m_14253225476704866645_1235880303.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_Detector_isim_beh.exe.sim/work/m_14253225476704866645_1235880303.didat b/isim/TEST_Detector_isim_beh.exe.sim/work/m_14253225476704866645_1235880303.didat Binary files differnew file mode 100644 index 0000000..ef16a5f --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/work/m_14253225476704866645_1235880303.didat diff --git a/isim/TEST_Detector_isim_beh.exe.sim/work/m_14253225476704866645_1235880303.lin64.o b/isim/TEST_Detector_isim_beh.exe.sim/work/m_14253225476704866645_1235880303.lin64.o Binary files differnew file mode 100644 index 0000000..ac1dc88 --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/work/m_14253225476704866645_1235880303.lin64.o diff --git a/isim/TEST_Detector_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c b/isim/TEST_Detector_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c new file mode 100644 index 0000000..0948290 --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c @@ -0,0 +1,337 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include <memory.h> +#ifdef __GNUC__ +#include <stdlib.h> +#else +#include <malloc.h> +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/verilog/src/glbl.v"; +static unsigned int ng1[] = {1U, 0U}; +static unsigned int ng2[] = {0U, 0U}; + + + +static void NetDecl_16_0(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + unsigned int t8; + unsigned int t9; + char *t10; + unsigned int t11; + unsigned int t12; + char *t13; + unsigned int t14; + unsigned int t15; + char *t16; + +LAB0: t1 = (t0 + 6952U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(16, ng0); + t2 = (t0 + 1960U); + t3 = *((char **)t2); + t2 = (t0 + 8640); + t4 = (t2 + 56U); + t5 = *((char **)t4); + t6 = (t5 + 56U); + t7 = *((char **)t6); + memset(t7, 0, 8); + t8 = 1U; + t9 = t8; + t10 = (t3 + 4); + t11 = *((unsigned int *)t3); + t8 = (t8 & t11); + t12 = *((unsigned int *)t10); + t9 = (t9 & t12); + t13 = (t7 + 4); + t14 = *((unsigned int *)t7); + *((unsigned int *)t7) = (t14 | t8); + t15 = *((unsigned int *)t13); + *((unsigned int *)t13) = (t15 | t9); + xsi_driver_vfirst_trans(t2, 0, 0U); + t16 = (t0 + 8512); + *((int *)t16) = 1; + +LAB1: return; +} + +static void Cont_48_1(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7200U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(48, ng0); + t2 = (t0 + 3640); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8704); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8528); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Cont_49_2(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7448U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(49, ng0); + t2 = (t0 + 3800); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8768); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8544); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Cont_50_3(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + char *t8; + char *t9; + unsigned int t10; + unsigned int t11; + char *t12; + unsigned int t13; + unsigned int t14; + char *t15; + unsigned int t16; + unsigned int t17; + char *t18; + +LAB0: t1 = (t0 + 7696U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(50, ng0); + t2 = (t0 + 3960); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 8832); + t6 = (t5 + 56U); + t7 = *((char **)t6); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memset(t9, 0, 8); + t10 = 1U; + t11 = t10; + t12 = (t4 + 4); + t13 = *((unsigned int *)t4); + t10 = (t10 & t13); + t14 = *((unsigned int *)t12); + t11 = (t11 & t14); + t15 = (t9 + 4); + t16 = *((unsigned int *)t9); + *((unsigned int *)t9) = (t16 | t10); + t17 = *((unsigned int *)t15); + *((unsigned int *)t15) = (t17 | t11); + xsi_driver_vfirst_trans(t5, 0, 0); + t18 = (t0 + 8560); + *((int *)t18) = 1; + +LAB1: return; +} + +static void Initial_52_4(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + +LAB0: t1 = (t0 + 7944U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(52, ng0); + +LAB4: xsi_set_current_line(53, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3640); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(54, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3960); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(55, ng0); + t2 = (t0 + 7752); + xsi_process_wait(t2, 100000LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(56, ng0); + t3 = ((char*)((ng2))); + t4 = (t0 + 3640); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + xsi_set_current_line(57, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 3960); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + goto LAB1; + +} + +static void Initial_60_5(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + +LAB0: t1 = (t0 + 8192U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(60, ng0); + +LAB4: xsi_set_current_line(61, ng0); + t2 = ((char*)((ng1))); + t3 = (t0 + 3800); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 1); + xsi_set_current_line(62, ng0); + t2 = (t0 + 8000); + xsi_process_wait(t2, 0LL); + *((char **)t1) = &&LAB5; + +LAB1: return; +LAB5: xsi_set_current_line(63, ng0); + t3 = ((char*)((ng2))); + t4 = (t0 + 3800); + xsi_vlogvar_assign_value(t4, t3, 0, 0, 1); + goto LAB1; + +} + + +extern void work_m_16541823861846354283_2073120511_init() +{ + static char *pe[] = {(void *)NetDecl_16_0,(void *)Cont_48_1,(void *)Cont_49_2,(void *)Cont_50_3,(void *)Initial_52_4,(void *)Initial_60_5}; + xsi_register_didat("work_m_16541823861846354283_2073120511", "isim/TEST_Detector_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat"); + xsi_register_executes(pe); +} diff --git a/isim/TEST_Detector_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat b/isim/TEST_Detector_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat Binary files differnew file mode 100644 index 0000000..9851841 --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat diff --git a/isim/TEST_Detector_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o b/isim/TEST_Detector_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o Binary files differnew file mode 100644 index 0000000..e862ecf --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o diff --git a/isim/isim_usage_statistics.html b/isim/isim_usage_statistics.html new file mode 100644 index 0000000..014f8a3 --- /dev/null +++ b/isim/isim_usage_statistics.html @@ -0,0 +1,5 @@ +<TABLE BORDER CELLSPACING=0 WIDTH='100%'> +<xtag-section name="ISimStatistics"> +<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR> +<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value></xtag-isim-property-value></TD></TR> +<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>1580 ms, 393016 KB</xtag-isim-property-value></TD></TR> diff --git a/isim/lockfile b/isim/lockfile new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/isim/lockfile diff --git a/isim/pn_info b/isim/pn_info new file mode 100644 index 0000000..c5644b4 --- /dev/null +++ b/isim/pn_info @@ -0,0 +1 @@ +13.4 diff --git a/isim/work/@detector.sdb b/isim/work/@detector.sdb Binary files differnew file mode 100644 index 0000000..327c706 --- /dev/null +++ b/isim/work/@detector.sdb diff --git a/isim/work/@t@e@s@t_@detector.sdb b/isim/work/@t@e@s@t_@detector.sdb Binary files differnew file mode 100644 index 0000000..e761685 --- /dev/null +++ b/isim/work/@t@e@s@t_@detector.sdb diff --git a/isim/work/glbl.sdb b/isim/work/glbl.sdb Binary files differnew file mode 100644 index 0000000..0075026 --- /dev/null +++ b/isim/work/glbl.sdb diff --git a/lab6.gise b/lab6.gise new file mode 100644 index 0000000..dd03494 --- /dev/null +++ b/lab6.gise @@ -0,0 +1,102 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="lab6.xise"/>
+
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xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> + <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> + <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> + <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> + <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> + <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> + <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> + <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> + <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> + <!-- --> + <!-- The following properties are for internal use only. These should not be modified.--> + <!-- --> + <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|TEST_Detector" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DesignName" xil_pn:value="lab6" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> + <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-03-27T20:33:10" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7B43AD5F81E13A08A76C7C95B2D5F889" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> + </properties> + + <bindings/> + + <libraries/> + + <autoManagedFiles> + <!-- The following files are identified by `include statements in verilog --> + <!-- source files and are automatically managed by Project Navigator. --> + <!-- --> + <!-- Do not hand-edit this section, as it will be overwritten when the --> + <!-- project is analyzed based on files automatically identified as --> + <!-- include files. --> + </autoManagedFiles> + +</project> diff --git a/xilinxsim.ini b/xilinxsim.ini new file mode 100644 index 0000000..600496d --- /dev/null +++ b/xilinxsim.ini @@ -0,0 +1 @@ +work=isim/work |